leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: SoC device tree updates for 4.16

Browse Source 
We get a moderate number of new machines this time, and only one
 new SoC variant (Actions S700):
 
 Actions:
   S700 Soc and CubieBoard7 development board
   Allo.com Sparky Single-board-computer
 
 Allwinner:
   Orange Pi R1 development board
   Libre Computer Board ALL-H3-CC H3 single-board computer
 
 ASpeed ast2x00:
    Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500
    Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500
    Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400
 
 AT91:
   Axentia Nattis/Natte digital signage
   sama5d2 PTC-ek Evaluation board
 
 Freescale/NXP i.MX:
    SolidRun Humminboard2 development board
    Variscite DART-MX6 SoM and Carrier-board
    Technologic TS-4600 and TS-7970 development board
    Toradex Colibri iMX7D SoM board
    v1.5 variant of Solidrun Cubox-i and Hummingboard
 
 Freescale/NXP Layerscape:
    Moxa UC-8410A Series industrial computer
 
 Gemini:
   D-Link DNS-313 NAS enclosure
 
 OMAP:
   LogicPD OMAP35xx SOM-LV devkit
   LogicPD OMAP35xx Torpedo devkit
 
 Renesas:
   r8a77970 (V3M) Starter Kit board
   r8a7795 (M3-W) Salvator-XS board
 
 We finally managed to get the dtc warnings under control, with no more
 build-time warnings for bad device tree files. This includes fixes for
 the majority of platforms, including nomadik, samsung, lpc32xx, STi,
 spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood,
 renesas, hisilicon, and broadcom.
 
 Files get rearranged on a few platforms, in particular the Marvell
 Armada 7K/8K device tree files are changed in preparation for future
 SoC support, based on more than two of the same chips in one package,
 and some boards get renamed for oxnas for consistency.
 
 Finally, many existing SoCs gain descriptions for additional on-chip
 devices that we can now support with kernel drivers:
 
   Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG)
   Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi)
   Aspeed clk controller support
   Freescale LS1088A, LS1021A device support
   Gemini Ethernet, PCI, TVE, panel
   Keystone gpio, qspi, more uarts
   Mediatek cpufreq, regulator, clock, reset
   Marvell thermal, cpufreq, nand
   Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu
   Rockchip Mipi, GPU, display
   Samsung Exynos5433 PMU, power domain, nfc
   Spreadtrum: sc9860 clocks
   Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ...
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJac0fiAAoJEGCrR//JCVInGUYP/ikTcjrmtQxmMINdsy88gmN3
 lPk3jGoViyRzc9Y6hGUUXn1YNdK8+IqRkqLnhtVX3cOLS5pP2HwsvSgPmSSB3eQe
 NOhXUNRQaTbeS/eBGZxJbxEKSowQHU+43M2kRNQOht7UQzS8NnBj/1RGaxcFyNSw
 gIixWDZLgVTNCSloPaSrZmiwSa7rSM2q0ncBzzeafAZiTRNeOb6IUpnqu/n0Qnot
 er6VoEyxp6ThFqRB7O8bCAIwgqlyB9xSGBPNR/JI0e0xXo3KVE/2AjHYDHVP/Ttx
 X8vtb3m+RED7tX4oCmlrHb1SAAKpNi1Vzdg4PxmKCa7yb5xPog7OEr3rnpijzCL0
 y8IJLlVSPyx31yB7mIIzCjrcISrT7tOXp0ha88/NgNsGXw5Ln0GVEqTkmSrz/JWo
 z1G2tNwnstS64KK+chHOZfUto4Rzbrpmr9L1ziKIpSQtiNyOmiSu1c3EjHim7x4I
 Mfiv6+8J71faUYuKVK1oaX0gi43oSZHu4NuniQy8dg/OIpgPpHHpG1qCyAzgC6Pa
 r1Am2w33CXrJI78b4zG2pIDx0HghIjFUtjX9tijoFiMs1EZgbV6cJ2meep6Sy+XV
 RBxHXPU8obdcuBfhgjEygwLI0HSe0R78B15qPP/SNxAFeAvE950xfPrGAoZg7qo/
 o6B2iQSfsYQJbD8rUHaA
 =qN1F
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates from Arnd Bergmann:
 "We get a moderate number of new machines this time, and only one new
  SoC variant (Actions S700):

  Actions:
   - S700 Soc and CubieBoard7 development board
   - Allo.com Sparky Single-board-computer

  Allwinner:
   - Orange Pi R1 development board
   - Libre Computer Board ALL-H3-CC H3 single-board computer

  ASpeed ast2x00:
   - Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500
   - Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500
   - Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400

  AT91:
   - Axentia Nattis/Natte digital signage
   - sama5d2 PTC-ek Evaluation board

  Freescale/NXP i.MX:
   - SolidRun Humminboard2 development board
   - Variscite DART-MX6 SoM and Carrier-board
   - Technologic TS-4600 and TS-7970 development board
   - Toradex Colibri iMX7D SoM board
   - v1.5 variant of Solidrun Cubox-i and Hummingboard

  Freescale/NXP Layerscape:
   - Moxa UC-8410A Series industrial computer

  Gemini:
   - D-Link DNS-313 NAS enclosure

  OMAP:
   - LogicPD OMAP35xx SOM-LV devkit
   - LogicPD OMAP35xx Torpedo devkit

  Renesas:
   - r8a77970 (V3M) Starter Kit board
   - r8a7795 (M3-W) Salvator-XS board

  We finally managed to get the dtc warnings under control, with no more
  build-time warnings for bad device tree files. This includes fixes for
  the majority of platforms, including nomadik, samsung, lpc32xx, STi,
  spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood,
  renesas, hisilicon, and broadcom.

  Files get rearranged on a few platforms, in particular the Marvell
  Armada 7K/8K device tree files are changed in preparation for future
  SoC support, based on more than two of the same chips in one package,
  and some boards get renamed for oxnas for consistency.

  Finally, many existing SoCs gain descriptions for additional on-chip
  devices that we can now support with kernel drivers:

   - Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG)
   - Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi)
   - Aspeed clk controller support
   - Freescale LS1088A, LS1021A device support
   - Gemini Ethernet, PCI, TVE, panel
   - Keystone gpio, qspi, more uarts
   - Mediatek cpufreq, regulator, clock, reset
   - Marvell thermal, cpufreq, nand
   - Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu
   - Rockchip Mipi, GPU, display
   - Samsung Exynos5433 PMU, power domain, nfc
   - Spreadtrum: sc9860 clocks
   - Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ..."

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (690 commits)
  arm64: dts: stratix10: fix SPI settings
  ARM: dts: socfpga: add i2c reset signals
  arm64: dts: stratix10: add USB ECC reset bit
  arm64: dts: stratix10: enable USB on the devkit
  ARM: dts: socfpga: disable over-current for Arria10 USB devkit
  ARM: dts: Nokia N9: add support for up/down keys in the dts
  ARM: dts: nomadik: add interrupt-parent for clcd
  ARM: dts: Add ethernet to a bunch of platforms
  ARM: dts: Add ethernet to the Gemini SoC
  ARM: dts: rename oxnas dts files
  ARM: dts: s5pv210: add interrupt-parent for ohci
  ARM: lpc3250: fix uda1380 gpio numbers
  ARM: dts: STi: Add gpio polarity for "hdmi,hpd-gpio" property
  ARM: dts: dra7: Reduce shut down temperature of non-cpu thermal zones
  ARM: dts: n900: Add aliases for lcd and tvout displays
  ARM: dts: Update ti-sysc data for existing users
  ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance
  arm64: dts: marvell: armada-80x0: Fix pinctrl compatible string
  arm: spear13xx: Fix spics gpio controller's warning
  arm: spear13xx: Fix dmas cells
  ...
This commit is contained in:
Linus Torvalds 2018-02-01 16:07:54 -08:00
commit 537433b624
576 changed files with 23183 additions and 7950 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/arm/actions.txt
View File

@ -21,10 +21,26 @@ Boards:
Root node property compatible must contain, depending on board:
- Allo.com Sparky: "allo,sparky"
- Cubietech CubieBoard6: "cubietech,cubieboard6"
- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
S700 SoC
========
Required root node properties:
- compatible : must contain "actions,s700"
Boards:
Root node property compatible must contain, depending on board:
- Cubietech CubieBoard7: "cubietech,cubieboard7"
S900 SoC
========

32
Documentation/devicetree/bindings/arm/atmel-at91.txt
View File

@ -90,38 +90,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
TC/TCLIB Timer required properties:
- compatible: Should be "atmel,<chip>-tcb".
<chip> can be "at91rm9200" or "at91sam9x5"
- reg: Should contain registers location and length
- interrupts: Should contain all interrupts for the TC block
Note that you can specify several interrupt cells if the TC
block has one interrupt per channel.
- clock-names: tuple listing input clock names.
Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks.
Examples:
One interrupt per TC block:
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 4>;
clocks = <&tcb0_clk>;
clock-names = "t0_clk";
};
One interrupt per TC channel in a TC block:
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffdc000 0x100>;
interrupts = <26 4 27 4 28 4>;
clocks = <&tcb1_clk>;
clock-names = "t0_clk";
};
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"

9
Documentation/devicetree/bindings/arm/axentia.txt
View File

@ -10,6 +10,15 @@ compatible = "axentia,linea",
and following the rules from atmel-at91.txt for a sama5d31 SoC.
Nattis v2 board with Natte v2 power board
-----------------------------------------
Required root node properties:
compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
and following the rules from above for the axentia,linea CPU module.
TSE-850 v3 board
----------------

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
View File

@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

4
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -104,12 +104,16 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7796"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- V3MSK
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"

11
Documentation/devicetree/bindings/arm/technologic.txt
View File

@ -1,6 +1,11 @@
Technologic Systems Platforms Device Tree Bindings
--------------------------------------------------
TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx28-ts4600", "fsl,imx28"
TS-4800 board
Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
@ -10,3 +15,9 @@ It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts7970", "fsl,imx6q"

36
Documentation/devicetree/bindings/bus/ti-sysc.txt
View File

@ -26,6 +26,8 @@ Required standard properties:
or one of the following derivative types for hardware
needing special workarounds:
"ti,sysc-omap2-timer"
"ti,sysc-omap4-timer"
"ti,sysc-omap3430-sr"
"ti,sysc-omap3630-sr"
"ti,sysc-omap4-sr"
@ -49,6 +51,26 @@ Required standard properties:
Optional properties:
- ti,sysc-mask shall contain mask of supported register bits for the
SYSCONFIG register as documented in the Technical Reference
Manual (TRM) for the interconnect target module
- ti,sysc-midle list of master idle modes supported by the interconnect
target module as documented in the TRM for SYSCONFIG
register MIDLEMODE bits
- ti,sysc-sidle list of slave idle modes supported by the interconnect
target module as documented in the TRM for SYSCONFIG
register SIDLEMODE bits
- ti,sysc-delay-us delay needed after OCP softreset before accssing
SYSCONFIG register again
- ti,syss-mask optional mask of reset done status bits as described in the
TRM for SYSSTATUS registers, typically 1 with some devices
having separate reset done bits for children like OHCI and
EHCI
- clocks clock specifier for each name in the clock-names as
specified in the binding documentation for ti-clkctrl,
typically available for all interconnect targets on TI SoCs
@ -61,6 +83,9 @@ Optional properties:
- ti,hwmods optional TI interconnect module name to use legacy
hwmod platform data
- ti,no-reset-on-init interconnect target module should not be reset at init
- ti,no-idle-on-init interconnect target module should not be idled at init
Example: Single instance of MUSB controller on omap4 using interconnect ranges
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;

7
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
View File

@ -5,8 +5,11 @@ controllers within the SoC.
Required Properties:
- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
or "amlogic,gxl-clkc" for GXL and GXM SoC.
- compatible: should be:
"amlogic,gxbb-clkc" for GXBB SoC,
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
- reg: physical base address of the clock controller and length of memory
mapped region.

41
Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt Normal file
View File

@ -0,0 +1,41 @@
Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel
==========================================================
The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel.
These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
with the following device-specific properties.
Required properties:
- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order.
Example
-------
panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
width-mm = <153>;
height-mm = <86>;
data-mapping = "jeida-18";
panel-timing {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <39>;
hfront-porch = <39>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <47>;
vsync-len = <2>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds_encoder>;
};
};
};

4
Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt
View File

@ -15,6 +15,10 @@ Required properties:
"de_be1-lcd1"
"de_be0-lcd0-hdmi"
"de_be1-lcd1-hdmi"
"mixer0-lcd0"
"mixer0-lcd0-hdmi"
"mixer1-lcd1-hdmi"
"mixer1-lcd1-tve"
Example:

2
Documentation/devicetree/bindings/dma/snps-dma.txt
View File

@ -64,6 +64,6 @@ Example:
reg = <0xe0000000 0x1000>;
interrupts = <0 35 0x4>;
dmas = <&dmahost 12 0 1>,
<&dmahost 13 0 1 0>;
<&dmahost 13 1 0>;
dma-names = "rx", "rx";
};

1
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
View File

@ -17,6 +17,7 @@ Required properties:
+ rockchip,rk3066-mali
+ rockchip,rk3188-mali
+ rockchip,rk3228-mali
+ rockchip,rk3328-mali
+ stericsson,db8500-mali
- reg: Physical base address and length of the GPU registers

2
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
View File

@ -12,6 +12,8 @@ Required properties:
- clock-names: Must include the following entries:
- mc: the module's clock input
- interrupts: The interrupt outputs from the controller.
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
the SWGROUP of the master.

56
Documentation/devicetree/bindings/mfd/atmel-tcb.txt Normal file
View File

@ -0,0 +1,56 @@
* Device tree bindings for Atmel Timer Counter Blocks
- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
<chip> can be "at91rm9200" or "at91sam9x5"
- reg: Should contain registers location and length
- #address-cells: has to be 1
- #size-cells: has to be 0
- interrupts: Should contain all interrupts for the TC block
Note that you can specify several interrupt cells if the TC
block has one interrupt per channel.
- clock-names: tuple listing input clock names.
Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks.
The TCB can expose multiple subdevices:
* a timer
- compatible: Should be "atmel,tcb-timer"
- reg: Should contain the TCB channels to be used. If the
counter width is 16 bits (at91rm9200-tcb), two consecutive
channels are needed. Else, only one channel will be used.
Examples:
One interrupt per TC block:
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 4>;
clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
One interrupt per TC channel in a TC block:
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffdc000 0x100>;
interrupts = <26 4>, <27 4>, <28 4>;
clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};

12
Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt Normal file
View File

@ -0,0 +1,12 @@
NVIDIA Tegra186 MISC register block
The MISC register block found on Tegra186 SoCs contains registers that can be
used to identify a given chip and various strapping options.
Required properties:
- compatible: Must be:
- Tegra186: "nvidia,tegra186-misc"
- reg: Should contain 2 entries: The first entry gives the physical address
and length of the register region which contains revision and debug
features. The second entry specifies the physical address and length
of the register region indicating the strapping options.

2
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
View File

@ -9,6 +9,8 @@ Required properties for the root node:
"amlogic,meson-gxbb-aobus-pinctrl"
"amlogic,meson-gxl-periphs-pinctrl"
"amlogic,meson-gxl-aobus-pinctrl"
"amlogic,meson-axg-periphs-pinctrl"
"amlogic,meson-axg-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===

2
Documentation/devicetree/bindings/power/actions,owl-sps.txt
View File

@ -2,10 +2,12 @@ Actions Semi Owl Smart Power System (SPS)
Required properties:
- compatible : "actions,s500-sps" for S500
"actions,s700-sps" for S700
- reg : Offset and length of the register set for the device.
- #power-domain-cells : Must be 1.
See macros in:
include/dt-bindings/power/owl-s500-powergate.h for S500
include/dt-bindings/power/owl-s700-powergate.h for S700
Example:

4
Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt
View File

@ -44,10 +44,10 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
pgc_pcie_phy: power-domain@3 {
pgc_pcie_phy: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
reg = <1>;
power-supply = <&reg_1p0d>;
};
};

2
Documentation/devicetree/bindings/power/ti-smartreflex.txt
View File

@ -7,7 +7,7 @@ Required properties:
compatible: Shall be one of the following:
"ti,omap3-smartreflex-core"
"ti,omap3-smartreflex-iva"
"ti,omap3-smartreflex-mpu-iva"
"ti,omap4-smartreflex-core"
"ti,omap4-smartreflex-mpu"
"ti,omap4-smartreflex-iva"

3
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt2712-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
- "mediatek,mt8173-scpsys"
@ -27,6 +29,7 @@ Required properties:
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -15,6 +15,7 @@ adi Analog Devices, Inc.
advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
allo Allo.com
allwinner Allwinner Technology Co., Ltd.
alphascale AlphaScale Integrated Circuits Systems, Inc.
altr Altera Corp.
@ -306,6 +307,7 @@ seagate Seagate Technology PLC
semtech Semtech Corporation
sensirion Sensirion AG
sff Small Form Factor Committee
sgd Solomon Goldentek Display Corporation
sgx SGX Sensortech
sharp Sharp Corporation
shimafuji Shimafuji Electric, Inc.

2
MAINTAINERS
View File

@ -2521,6 +2521,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/axentia.txt
F: arch/arm/boot/dts/at91-linea.dtsi
F: arch/arm/boot/dts/at91-natte.dtsi
F: arch/arm/boot/dts/at91-nattis-2-natte-2.dts
F: arch/arm/boot/dts/at91-tse850-3.dts
AXENTIA ASOC DRIVERS

1
arch/arm/Kconfig
View File

@ -596,6 +596,7 @@ config ARCH_S3C24XX
select MULTI_IRQ_HANDLER
select NEED_MACH_IO_H
select SAMSUNG_ATAGS
select USE_OF
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST

47
arch/arm/boot/dts/Makefile
View File

@ -1,6 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
ifeq ($(CONFIG_OF),y)
dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
dtb-$(CONFIG_MACH_ARTPEC6) += \
@ -47,7 +45,9 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
at91-tse850-3.dtb \
@ -192,6 +192,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dir-685.dtb \
gemini-dlink-dns-313.dtb \
gemini-nas4220b.dtb \
gemini-rut1xx.dtb \
gemini-sq201.dtb \
@ -372,6 +373,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos2_7.dtb \
imx6dl-colibri-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
@ -384,6 +387,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
imx6dl-hummingboard2.dtb \
imx6dl-hummingboard2-emmc-som-v15.dtb \
imx6dl-hummingboard2-som-v15.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-nit6xlite.dtb \
@ -396,6 +404,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabresd.dtb \
imx6dl-savageboard.dtb \
imx6dl-ts4900.dtb \
imx6dl-ts7970.dtb \
imx6dl-tx6dl-comtft.dtb \
imx6dl-tx6s-8034.dtb \
imx6dl-tx6s-8034-mb7.dtb \
@ -421,6 +430,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-b850v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
imx6q-cubox-i-som-v15.dtb \
imx6q-dfi-fs700-m60.dtb \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
@ -439,6 +450,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw5904.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
imx6q-hummingboard-som-v15.dtb \
imx6q-hummingboard2.dtb \
imx6q-hummingboard2-emmc-som-v15.dtb \
imx6q-hummingboard2-som-v15.dtb \
imx6q-icore.dtb \
imx6q-icore-ofcap10.dtb \
imx6q-icore-ofcap12.dtb \
@ -459,6 +475,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-sbc6x.dtb \
imx6q-tbs2910.dtb \
imx6q-ts4900.dtb \
imx6q-ts7970.dtb \
imx6q-tx6q-1010.dtb \
imx6q-tx6q-1010-comtft.dtb \
imx6q-tx6q-1020.dtb \
@ -470,6 +487,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-tx6q-11x0-mb7.dtb \
imx6q-udoo.dtb \
imx6q-utilite-pro.dtb \
imx6q-var-dt6customboard.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
@ -511,15 +529,17 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
imx7d-pico.dtb \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_SOC_VF610) += \
@ -558,6 +578,7 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx28-m28cu3.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
imx28-ts4600.dtb \
imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += \
ste-nomadik-s8815.dtb \
@ -689,6 +710,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
am571x-idk.dtb \
am574x-idk.dtb \
dra7-evm.dtb \
dra72-evm.dtb \
dra72-evm-revc.dtb \
@ -707,12 +729,13 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-rd88f5182-nas.dtb
dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-cubieboard6.dtb \
owl-s500-guitar-bb-rev-b.dtb
owl-s500-guitar-bb-rev-b.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
wd-mbwe.dtb \
cloudengines-pogoplug-series-3.dtb
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
@ -756,6 +779,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
@ -949,9 +973,11 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-bananapi-m3.dtb \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dtb \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
@ -1101,7 +1127,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-ast2500-evb.dtb
endif
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-quanta-q71l.dtb

2
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -409,6 +409,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

81
arch/arm/boot/dts/am335x-boneblue.dts
View File

@ -159,6 +159,7 @@
>;
};
/* UT0 */
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
@ -166,6 +167,37 @@
>;
};
/* UT1 */
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */
>;
};
/* GPS */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (B17) spi0_d0.uart2_txd */
>;
};
/* DSM2 */
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */
>;
};
/* UT5 */
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8C4, PIN_INPUT_PULLUP | MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */
AM33XX_IOPAD(0x8C0, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* (U1) lcd_data8.uart5_txd */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
@ -216,10 +248,19 @@
wl18xx_pins: pinmux_wl18xx_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
>;
};
/* DCAN */
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */
AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
>;
};
};
&uart0 {
@ -229,6 +270,34 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
status = "okay";
};
&usb {
status = "okay";
};
@ -414,7 +483,7 @@
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio0>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
};
};
@ -446,10 +515,16 @@
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};
&gpio3 {
ls_buf_en {
gpio-hog;

2
arch/arm/boot/dts/am335x-evm.dts
View File

@ -790,6 +790,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -722,6 +722,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-pepper.dts
View File

@ -139,7 +139,7 @@
&audio_codec {
status = "okay";
gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
AVDD-supply = <&ldo3_reg>;
IOVDD-supply = <&ldo3_reg>;
DRVDD-supply = <&ldo3_reg>;

205
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -292,14 +292,6 @@
clock-div = <4>;
};
cefuse_fck: cefuse_fck@a20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <1>;
reg = <0x0a20>;
};
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -316,14 +308,6 @@
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick@14c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <1>;
reg = <0x014c>;
};
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -350,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@ -423,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@ -493,42 +477,10 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
gpio0_dbclk: gpio0_dbclk@408 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <18>;
reg = <0x0408>;
};
gpio1_dbclk: gpio1_dbclk@ac {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00ac>;
};
gpio2_dbclk: gpio2_dbclk@b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b0>;
};
gpio3_dbclk: gpio3_dbclk@b4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b4>;
};
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -577,58 +529,6 @@
reg = <0x0700>;
};
dbg_sysclk_ck: dbg_sysclk_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <19>;
reg = <0x0414>;
};
dbg_clka_ck: dbg_clka_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <30>;
reg = <0x0414>;
};
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <22>;
reg = <0x0414>;
};
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <20>;
reg = <0x0414>;
};
stm_clk_div_ck: stm_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&stm_pmd_clock_mux_ck>;
ti,bit-shift = <27>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
trace_clk_div_ck: trace_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&trace_pmd_clk_mux_ck>;
ti,bit-shift = <24>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@ -638,9 +538,88 @@
};
};
&prcm_clockdomains {
clk_24mhz_clkdm: clk_24mhz_clkdm {
compatible = "ti,clockdomain";
clocks = <&clkdiv32k_ick>;
&prcm {
l4_per_cm: l4_per_cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
l4_per_clkctrl: clk@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
};

18
arch/arm/boot/dts/am33xx.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
@ -179,8 +180,11 @@
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -496,7 +500,7 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
@ -517,6 +521,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -524,6 +530,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
@ -571,7 +579,7 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&clkdiv32k_ick>;
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
@ -991,7 +999,7 @@
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803C000 {
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
@ -1014,4 +1022,4 @@
};
};
/include/ "am33xx-clocks.dtsi"
#include "am33xx-clocks.dtsi"

8
arch/arm/boot/dts/am3517.dtsi
View File

@ -26,7 +26,7 @@
interrupt-names = "mc";
};
davinci_emac: ethernet@0x5c000000 {
davinci_emac: ethernet@5c000000 {
compatible = "ti,am3517-emac";
ti,hwmods = "davinci_emac";
status = "disabled";
@ -41,7 +41,7 @@
local-mac-address = [ 00 00 00 00 00 00 ];
};
davinci_mdio: ethernet@0x5c030000 {
davinci_mdio: ethernet@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
@ -99,9 +99,5 @@
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

20
arch/arm/boot/dts/am4372.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
/ {
compatible = "ti,am4372", "ti,am43";
@ -163,9 +164,12 @@
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -325,7 +329,7 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@ -346,6 +350,8 @@
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -353,6 +359,8 @@
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
@ -936,7 +944,7 @@
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803C000 {
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
@ -993,7 +1001,7 @@
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
<&usb_otg_ss0_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@ -1012,7 +1020,7 @@
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@ -1175,4 +1183,4 @@
};
};
/include/ "am43xx-clocks.dtsi"
#include "am43xx-clocks.dtsi"

4
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -55,7 +55,7 @@
enable-active-high;
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -86,6 +86,8 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;

14
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -519,3 +519,17 @@
&cpu {
cpu0-supply = <&tps>;
};
&cpu0_opp_table {
/*
* Supply voltage supervisor on board will not allow opp50 so
* disable it and set opp100 as suspend OPP.
*/
opp50@300000000 {
status = "disabled";
};
opp100@600000000 {
opp-suspend;
};
};

4
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -35,7 +35,7 @@
clock-frequency = <32768>;
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -132,6 +132,8 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
backlight = <&lcd_bl>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
panel-timing {

10
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -48,6 +48,8 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@ -107,7 +109,7 @@
0x03030069>; /* LEFT */
};
backlight {
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -985,7 +987,11 @@
rx-num-evt = <32>;
};
&synctimer_32kclk {
&mux_synctimer32k_ck {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
&cpu {
cpu0-supply = <&dcdc2>;
};

212
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -524,54 +524,6 @@
reg = <0x4240>;
};
gpio0_dbclk: gpio0_dbclk@2b68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <8>;
reg = <0x2b68>;
};
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c78>;
};
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c80>;
};
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c88>;
};
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c90>;
};
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c98>;
};
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -629,14 +581,6 @@
reg = <0x4230>;
};
synctimer_32kclk: synctimer_32kclk@2a30 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&mux_synctimer32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a30>;
};
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -763,110 +707,76 @@
ti,bit-shift = <8>;
reg = <0x2a48>;
};
};
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a60>;
&prcm {
l4_wkup_cm: l4_wkup_cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x34c>;
#clock-cells = <2>;
};
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a68>;
mpu_cm: mpu_cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_osc_div_ck: clkout1_osc_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
gfx_l3_cm: gfx_l3_cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
gfx_l3_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_src2_mux_ck: clkout1_src2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
l4_rtc_cm: l4_rtc_cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
l4_rtc_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
l4_per_cm: l4_per_cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
clkout2_src_mux_ck: clkout2_src_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
reg = <0x4108>;
};
clkout2_pre_div_ck: clkout2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_src_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4108>;
};
clkout2_post_div_ck: clkout2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4108>;
};
clkout2_ck: clkout2_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout2_post_div_ck>;
ti,bit-shift = <16>;
reg = <0x4108>;
l4_per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xb04>;
#clock-cells = <2>;
};
};
};

4
arch/arm/boot/dts/am571x-idk.dts
View File

@ -117,3 +117,7 @@
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

100
arch/arm/boot/dts/am572x-idk-common.dtsi Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
/ {
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
cpu1-led {
label = "status1:red:cpu1";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu1";
};
usr1-led {
label = "status1:green:usr";
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

93
arch/arm/boot/dts/am572x-idk.dts
View File

@ -9,8 +9,7 @@
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
@ -18,54 +17,6 @@
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
cpu1-led {
label = "status1:red:cpu1";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu1";
};
usr1-led {
label = "status1:green:usr";
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
};
&mmc1 {
@ -86,44 +37,6 @@
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

22
arch/arm/boot/dts/am574x-idk.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "dra76x.dtsi"
#include "am572x-idk-common.dtsi"
/ {
model = "TI AM5748 IDK";
compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
};
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
spi-max-frequency = <96000000>;
};
};

4
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -388,7 +388,7 @@
};
&cpu0 {
cpu0-supply = <&smps12_reg>;
vdd-supply = <&smps12_reg>;
voltage-tolerance = <1>;
};
@ -554,7 +554,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

12
arch/arm/boot/dts/animeo_ip.dts
View File

@ -43,6 +43,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fffb0000 {
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
linux,rs485-enabled-at-boot-time;

5
arch/arm/boot/dts/arm-realview-eb-mp.dtsi
View File

@ -150,11 +150,6 @@
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
};
&charlcd {
interrupt-parent = <&intc>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
&serial0 {
interrupt-parent = <&intc>;
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;

5
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -279,6 +279,11 @@
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";

4
arch/arm/boot/dts/aspeed-ast2500-evb.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
@ -16,7 +16,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};

5
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g4.dtsi"
@ -12,7 +12,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@ -34,6 +34,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};

135
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
View File

@ -1,23 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Romulus BMC";
compatible = "ibm,romulus-bmc", "aspeed,ast2500";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
reg = <0x80000000 0x40000000>;
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
@ -29,6 +25,49 @@
no-map;
reg = <0xbf000000 0x01000000>; /* 16M */
};
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
leds {
compatible = "gpio-leds";
fault {
gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
};
identify {
gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
power {
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
};
};
@ -38,6 +77,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
@ -53,6 +93,12 @@
};
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
@ -81,6 +127,10 @@
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
@ -133,8 +183,77 @@
&i2c12 {
status = "okay";
max31785@52 {
compatible = "maxim,max31785";
reg = <0x52>;
};
};
&gpio {
nic_func_mode0 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "nic_func_mode0";
};
nic_func_mode1 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "nic_func_mode1";
};
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@2 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@3 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
fan@4 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
};
fan@5 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
};
fan@6 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
};

548
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts Normal file
View File

@ -0,0 +1,548 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Witherspoon BMC";
compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
label = "fan0-presence";
gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
};
leds {
compatible = "gpio-leds";
fan0 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
};
fan1 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
};
fan2 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
};
fan3 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
};
front-fault {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
};
front-power {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
};
front-id {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
};
rear-fault {
gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
};
rear-id {
gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
};
rear-power {
gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
};
power-button {
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
iio-hwmon-dps310 {
compatible = "iio-hwmon";
io-channels = <&dps 0>;
};
iio-hwmon-bmp280 {
compatible = "iio-hwmon";
io-channels = <&bmp 1>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
label = "alt";
m25p,fast-read;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart2 {
/* APSS */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
};
&uart5 {
status = "okay";
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&i2c2 {
status = "okay";
/* MUX ->
* Samtec 1
* Samtec 2
*/
};
&i2c3 {
status = "okay";
bmp: bmp280@77 {
compatible = "bosch,bmp280";
reg = <0x77>;
#io-channel-cells = <1>;
};
max31785@52 {
compatible = "maxim,max31785a";
reg = <0x52>;
#address-cells = <1>;
#size-cells = <0>;
};
dps: dps310@76 {
compatible = "infineon,dps310";
reg = <0x76>;
#io-channel-cells = <0>;
};
pca0: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
power-supply@68 {
compatible = "ibm,cffps1";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps1";
reg = <0x69>;
};
};
&i2c4 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c5 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c9 {
status = "okay";
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
};
&i2c10 {
/* MUX
* -> PCIe Slot 3
* -> PCIe Slot 4
*/
status = "okay";
};
&i2c11 {
status = "okay";
pca9552: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
"GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
"GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
"GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
"GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
"GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
"GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
"12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
eeprom@51 {
compatible = "atmel,24c64";
reg = <0x51>;
};
ucd90160@64 {
compatible = "ti,ucd90160";
reg = <0x64>;
};
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
};

426
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts Normal file
View File

@ -0,0 +1,426 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Zaius BMC";
compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
};
onewire0 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
};
onewire1 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
};
onewire2 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
onewire3 {
compatible = "w1-gpio";
gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 7)>;
};
};
leds {
compatible = "gpio-leds";
sys_boot_status {
label = "System boot status";
gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
};
attention {
label = "Attention";
gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
};
plt_fault {
label = "Platform fault";
gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
};
hdd_fault {
label = "Onboard drive fault";
gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 13>, <&adc 14>, <&adc 15>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 12>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2ck_default
&pinctrl_spi2cs0_default
&pinctrl_spi2cs1_default
&pinctrl_spi2miso_default
&pinctrl_spi2mosi_default>;
flash@0 {
status = "okay";
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
ucd90160@64 {
compatible = "ti,ucd90160";
reg = <0x64>;
};
/* Power sequencer UCD90160 PMBUS @64h
* FRU AT24C64D @50h
* RTC PCF8523 @68h
* Clock buffer 9DBL04 @6dh
*/
};
&i2c1 {
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
};
/* MUX1 PCA9546A @71h
* PCIe 0
* PCIe 1
* PCIe 2
* TPM header
*/
};
&i2c2 {
status = "disabled";
/* OCP Mezz Connector A (OOB SMBUS) */
};
&i2c3 {
status = "disabled";
/* OCP Mezz Connector A (PCIe slot SMBUS) */
};
&i2c4 {
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
};
/* MUX1 PCA9546A @71h
* PCIe 3
* PCIe 4
*/
};
&i2c5 {
status = "disabled";
/* CPU0 PRM 0.7V */
/* CPU0 PRM 1.2V CH03 */
/* CPU0 PRM 0.8V */
/* CPU0 PRM 1.2V CH47 */
};
&i2c6 {
status = "disabled";
/* CPU1 PRM 0.7V */
/* CPU1 PRM 1.2V CH03 */
/* CPU1 PRM 0.8V */
/* CPU1 PRM 1.2V CH47 */
};
&i2c7 {
status = "okay";
pca9541a@70 {
compatible = "nxp,pca9541";
reg = <0x70>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
hotswap@54 {
compatible = "ti,lm5066i";
reg = <0x54>;
};
};
};
/* Master selector PCA9541A @70h (other master: CPU0)
* LM5066I PMBUS @10h
*/
/* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
power-brick@61 {
compatible = "delta,dps800";
reg = <0x61>;
};
/* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
/* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
/* CPU0 VR ISL68137 0.8V PMBUS @60h */
/* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
/* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
};
&i2c8 {
status = "okay";
/* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
/* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
/* CPU1 VR ISL68137 0.8V PMBUS @61h */
/* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
/* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
};
&i2c9 {
status = "disabled";
/* Fan board */
};
&i2c10 {
status = "disabled";
};
&i2c11 {
status = "disabled";
/* GPU sideband */
};
&i2c12 {
status = "disabled";
};
&i2c13 {
status = "disabled";
/* MUX PI3USB102
* CPU0 debug
* CPU1 debug
*/
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
pinctrl_gpioh_unbiased: gpioi_unbiased {
pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
bias-disable;
};
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioh_unbiased>;
line_iso_u146_en {
gpio-hog;
gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "iso_u164_en";
};
ncsi_mux_en_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "ncsi_mux_en_n";
};
line_bmc_i2c2_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "bmc_i2c2_sw_rst_n";
};
line_bmc_i2c5_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "bmc_i2c5_sw_rst_n";
};
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
};

458
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts Normal file
View File

@ -0,0 +1,458 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g4.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Quanta Q71L BMC";
compatible = "quanta,q71l-bmc", "aspeed,ast2400";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@40000000 {
reg = <0x40000000 0x8000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@47800000 {
no-map;
reg = <0x47800000 0x00800000>; /* 8MB */
};
};
leds {
compatible = "gpio-leds";
heartbeat {
gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
};
power {
gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
};
identify {
gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 11>;
};
i2c1mux: i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
i2c-parent = <&i2c1>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&uart5 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
/* temp2 inlet */
tmp75@4c {
compatible = "ti,tmp75";
reg = <0x4c>;
};
/* temp3 */
tmp75@4e {
compatible = "ti,tmp75";
reg = <0x4e>;
};
/* temp1 */
tmp75@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
/* Baseboard FRU */
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
};
/* FP FRU */
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
&i2c2 {
status = "okay";
/* 0: PCIe Slot 2,
* Slot 3,
* Slot 6,
* Slot 7
*/
i2c-switch@74 {
compatible = "nxp,pca9546";
reg = <0x74>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect; /* may use mux@77 next. */
i2c_pcie2: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_pcie3: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_pcie6: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_pcie7: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
/* 0: PCIe Slot 1,
* Slot 4,
* Slot 5,
* Slot 8,
* Slot 9,
* Slot 10,
* SSD 1,
* SSD 2
*/
i2c-switch@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c-mux-idle-disconnect; /* may use mux@74 next. */
i2c_pcie1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_pcie4: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_pcie5: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_pcie8: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c_pcie9: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c_pcie10: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c_ssd1: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c_ssd2: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c3 {
status = "okay";
/* BIOS FRU */
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
/* 0: PSU4
* PSU1
* PSU3
* PSU2
*/
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c_psu4: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_psu1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_psu3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_psu2: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
/* PDB FRU */
eeprom@52 {
compatible = "atmel,24c64";
reg = <0x52>;
};
};
&i2c8 {
status = "okay";
/* BMC FRU */
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
&vuart {
status = "okay";
};
&wdt2 {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm2_default
&pinctrl_pwm3_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&i2c1mux {
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
/* Memory Riser 1 FRU */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* Memory Riser 2 FRU */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* Memory Riser 3 FRU */
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
};
/* Memory Riser 4 FRU */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Memory Riser 5 FRU */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* Memory Riser 6 FRU */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* Memory Riser 7 FRU */
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
};
/* Memory Riser 8 FRU */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
};

163
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@ -69,6 +70,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -89,6 +91,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@ -96,6 +99,7 @@
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
@ -106,47 +110,12 @@
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
clk_clkin: clk_clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
clk_hpll: clk_hpll@70 {
#clock-cells = <0>;
compatible = "aspeed,g4-hpll-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_clkin>;
clock-frequency = <384000000>;
};
clk_ahb: clk_ahb@70 {
#clock-cells = <0>;
compatible = "aspeed,g4-ahb-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_hpll>;
clock-frequency = <192000000>;
};
clk_apb: clk_apb@8 {
#clock-cells = <0>;
compatible = "aspeed,g4-apb-clock", "fixed-clock";
reg = <0x08>;
clocks = <&clk_hpll>;
clock-frequency = <48000000>;
};
clk_uart: clk_uart@2c{
#clock-cells = <0>;
compatible = "aspeed,g4-uart-clock", "fixed-clock";
reg = <0x2c>;
clock-frequency = <24000000>;
};
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g4-pinctrl";
@ -156,7 +125,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2400-adc";
reg = <0x1e6e9000 0xb0>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@ -173,6 +143,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
@ -181,7 +152,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@ -190,7 +161,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@ -200,7 +171,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@ -208,11 +179,23 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785020 0x1c>;
clocks = <&syscon ASPEED_CLK_APB>;
};
pwm_tacho: pwm-tacho-controller@1e786000 {
compatible = "aspeed,ast2400-pwm-tacho";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
vuart: serial@1e787000 {
@ -220,17 +203,59 @@
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2400-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc@0 {
compatible = "aspeed,ast2400-lpc-bmc";
reg = <0x0 0x80>;
};
lpc_host: lpc-host@80 {
compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
reg = <0x80 0x1e0>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2400-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
};
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@ -240,7 +265,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@ -250,7 +275,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@ -281,7 +306,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@ -296,7 +322,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@ -311,7 +338,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@ -327,7 +355,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@ -343,7 +372,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@ -359,7 +389,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@ -375,7 +406,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@ -391,7 +423,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@ -407,7 +440,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@ -423,7 +457,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@ -439,7 +474,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@ -455,7 +491,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@ -471,7 +508,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@ -487,7 +525,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;

156
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
/ {
model = "Aspeed BMC";
@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
interrupts = <19>;
flash@0 {
@ -79,6 +80,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -98,6 +100,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
clocks = <&syscon ASPEED_CLK_AHB>;
status = "disabled";
flash@0 {
reg = < 0 >;
@ -123,6 +126,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
status = "disabled";
};
@ -130,6 +134,7 @@
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
status = "disabled";
};
@ -140,55 +145,18 @@
ranges;
syscon: syscon@1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
clk_clkin: clk_clkin@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-clkin-clock", "fixed-clock";
reg = <0x70>;
clock-frequency = <24000000>;
};
clk_hpll: clk_hpll@24 {
#clock-cells = <0>;
compatible = "aspeed,g5-hpll-clock", "fixed-clock";
reg = <0x24>;
clocks = <&clk_clkin>;
clock-frequency = <792000000>;
};
clk_ahb: clk_ahb@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-ahb-clock", "fixed-clock";
reg = <0x70>;
clocks = <&clk_hpll>;
clock-frequency = <198000000>;
};
clk_apb: clk_apb@8 {
#clock-cells = <0>;
compatible = "aspeed,g5-apb-clock", "fixed-clock";
reg = <0x08>;
clocks = <&clk_hpll>;
clock-frequency = <24750000>;
};
clk_uart: clk_uart@2c {
#clock-cells = <0>;
compatible = "aspeed,uart-clock", "fixed-clock";
reg = <0x2c>;
clock-frequency = <24000000>;
};
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
};
gfx: display@1e6e6000 {
@ -200,7 +168,8 @@
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_ADC>;
#io-channel-cells = <1>;
status = "disabled";
};
@ -217,6 +186,7 @@
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
};
@ -225,7 +195,7 @@
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
clock-names = "PCLK";
};
@ -234,7 +204,7 @@
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
no-loopback-test;
status = "disabled";
};
@ -244,7 +214,7 @@
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
no-loopback-test;
status = "disabled";
};
@ -252,16 +222,39 @@
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
};
wdt3: watchdog@1e785040 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785040 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
};
pwm_tacho: pwm-tacho-controller@1e786000 {
compatible = "aspeed,ast2500-pwm-tacho";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
status = "disabled";
};
@ -288,6 +281,19 @@
reg-io-width = <4>;
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
@ -295,22 +301,12 @@
};
};
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <10>;
clocks = <&clk_uart>;
no-loopback-test;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
no-loopback-test;
status = "disabled";
};
@ -320,7 +316,7 @@
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
no-loopback-test;
status = "disabled";
};
@ -330,7 +326,7 @@
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
clocks = <&clk_uart>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
no-loopback-test;
status = "disabled";
};
@ -361,7 +357,8 @@
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
@ -376,7 +373,8 @@
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
@ -391,7 +389,8 @@
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
@ -407,7 +406,8 @@
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
@ -423,7 +423,8 @@
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
@ -439,7 +440,8 @@
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
@ -455,7 +457,8 @@
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
@ -471,7 +474,8 @@
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
@ -487,7 +491,8 @@
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
@ -503,7 +508,8 @@
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
@ -519,7 +525,8 @@
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
@ -535,7 +542,8 @@
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
@ -551,7 +559,8 @@
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
@ -567,7 +576,8 @@
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
clocks = <&clk_apb>;
clocks = <&syscon ASPEED_CLK_APB>;
resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;

12
arch/arm/boot/dts/at91-ariag25.dts
View File

@ -58,6 +58,18 @@
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f8010000 {
status = "okay";
};

12
arch/arm/boot/dts/at91-ariettag25.dts
View File

@ -46,6 +46,18 @@
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usb2: gadget@f803c000 {
status = "okay";
};

12
arch/arm/boot/dts/at91-cosino.dtsi
View File

@ -37,6 +37,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_board_mmc0

12
arch/arm/boot/dts/at91-foxg20.dts
View File

@ -34,6 +34,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
status = "okay";

12
arch/arm/boot/dts/at91-kizbox.dts
View File

@ -31,6 +31,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii

12
arch/arm/boot/dts/at91-kizbox2.dts
View File

@ -94,6 +94,18 @@
};
};
tcb0: timer@f0010000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usart0: serial@f001c000 {
status = "okay";
};

12
arch/arm/boot/dts/at91-kizboxmini.dts
View File

@ -34,6 +34,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usart0: serial@f801c000 {
status = "okay";
};

12
arch/arm/boot/dts/at91-linea.dtsi
View File

@ -27,6 +27,18 @@
clock-frequency = <12000000>;
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&i2c0 {
status = "okay";

244
arch/arm/boot/dts/at91-natte.dtsi Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* at91-natte.dts - Device Tree include file for the Natte board
*
* Copyright (C) 2017 Axentia Technologies AB
*
* Author: Peter Rosin <peda@axentia.se>
*/
/ {
mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
<&ioexp 1 GPIO_ACTIVE_HIGH>,
<&ioexp 2 GPIO_ACTIVE_HIGH>;
};
batntc-mux {
compatible = "io-channel-mux";
io-channels = <&adc 5>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"batntc0", "batntc1", "batntc2", "batntc3",
"batntc4", "batntc5", "batntc6", "batntc7";
};
batv-mux {
compatible = "io-channel-mux";
io-channels = <&adc 6>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"batv0", "batv1", "batv2", "batv3",
"batv4", "batv5", "batv6", "batv7";
};
iout-mux {
compatible = "io-channel-mux";
io-channels = <&adc 7>;
io-channel-names = "parent";
mux-controls = <&mux>;
channels =
"iout0", "iout1", "iout2", "iout3",
"iout4", "iout5", "iout6", "iout7";
};
i2c-mux {
compatible = "i2c-mux";
mux-locked;
i2c-parent = <&i2c0>;
mux-controls = <&mux>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
charger@9 {
compatible = "ti,bq24735";
reg = <0x9>;
ti,charge-current = <2000>;
ti,charge-voltage = <16800>;
poll-interval = <20000>;
};
};
};
};
&i2c0 {
status = "okay";
ioexp: ioexp@20 {
#gpio-cells = <2>;
compatible = "semtech,sx1502q";
reg = <0x20>;
gpio-controller;
ngpios = <8>;
pinctrl-names = "default";
pinctrl-0 = <&gpio3_cfg_pins>;
gpio3_cfg_pins: gpio3_cfg {
pins = "gpio3";
bias-pull-up;
};
};
adc: adc@48 {
compatible = "ti,ads1015";
reg = <0x48>;
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
ti,gain = <2>;
ti,datarate = <4>;
};
channel@5 {
reg = <5>;
ti,gain = <2>;
ti,datarate = <4>;
};
channel@6 {
reg = <6>;
ti,gain = <1>;
ti,datarate = <4>;
};
channel@7 {
reg = <7>;
ti,gain = <3>;
ti,datarate = <4>;
};
};
};

258
arch/arm/boot/dts/at91-nattis-2-natte-2.dts Normal file
View File

@ -0,0 +1,258 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
*
* Copyright (C) 2017 Axentia Technologies AB
*
* Author: Peter Rosin <peda@axentia.se>
*/
/dts-v1/;
#include "at91-linea.dtsi"
#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {
model = "Axentia Linea-Nattis v2 Natte v2";
compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
pinctrl@fffff200 {
nattis {
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOD 28
AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOD 5
AT91_PERIPH_GPIO
AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_lcd_prlud0: lcd_prlud0 {
atmel,pins =
<AT91_PIOA 21
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
pinctrl_lcd_hipow0: lcd_hipow0 {
atmel,pins =
<AT91_PIOA 23
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
};
};
watchdog@fffffe40 {
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
wakeup {
label = "Wakeup";
linux,code = <10>;
gpio-key,wakeup;
gpios = <&pioB 27 GPIO_ACTIVE_LOW>;
};
};
panel_reg: panel-regulator {
compatible = "regulator-fixed";
regulator-name = "panel-VCC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
bl_reg: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "panel-VDD";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
panel_bl: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 100000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <40>;
power-supply = <&bl_reg>;
enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "sharp,lq150x1lg11";
backlight = <&panel_bl>;
power-supply = <&panel_reg>;
port {
panel_input: endpoint {
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "nattis-tfa9879";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&cpu_dai>;
simple-audio-card,frame-master = <&cpu_dai>;
simple-audio-card,widgets = "Line", "Line Out Jack";
simple-audio-card,routing = "Line Out Jack", "LINEOUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssc0>;
};
simple-audio-card,codec {
sound-dai = <&amp>;
};
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
temp@18 {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x18>;
smbus-timeout-disable;
};
eeprom@50 {
compatible = "nxp,24c02";
reg = <0x50>;
pagesize = <16>;
};
amp: amplifier@6c {
compatible = "nxp,tfa9879";
reg = <0x6c>;
#sound-dai-cells = <0>;
};
};
&ssc0 {
status = "okay";
atmel,clk-from-rk-pin;
#sound-dai-cells = <0>;
};
&hlcdc {
status = "okay";
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base
&pinctrl_lcd_rgb565
&pinctrl_lcd_prlud0
&pinctrl_lcd_hipow0>;
port@0 {
hlcdc_panel_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
&mmc0 {
status = "okay";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
&pinctrl_mmc0_dat1_3
&pinctrl_mmc0_cd>;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
};
};
&usart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
atmel,use-dma-rx;
};
&nand {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
};
bootloaderenv@c0000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
&dbgu {
status = "okay";
atmel,use-dma-rx;
};
&usb0 {
status = "okay";
atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
};

12
arch/arm/boot/dts/at91-qil_a9260.dts
View File

@ -31,6 +31,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";

12
arch/arm/boot/dts/at91-sam9_l9260.dts
View File

@ -32,6 +32,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
mmc0: mmc@fffa8000 {
pinctrl-0 = <
&pinctrl_board_mmc0

12
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -119,6 +119,18 @@
status = "okay";
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;

413
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts Normal file
View File

@ -0,0 +1,413 @@
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
*
* Copyright (C) 2017 Microchip/Atmel,
* 2017 Wenyou Yang <wenyou.yang@microchip.com>
* 2017 Ludovic Desroches <ludovic.desroches@microchip.com>
*/
/dts-v1/;
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D2 PTC EK";
compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
ahb {
usb0: gadget@300000 {
atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
usb1: ohci@400000 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PB12 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
usb2: ehci@500000 {
status = "okay";
};
ebi: ebi@10000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_default>;
status = "okay"; /* conflicts with sdmmc1 and qspi0 */
nand_controller: nand-controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenv@0x100000 {
label = "bootloader env";
reg = <0x100000 0x40000>;
};
bootloaderenvred@0x140000 {
label = "bootloader env redundant";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
non-removable;
mmc-ddr-1_8v;
status = "okay";
};
apb {
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioA>;
interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
};
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
uart0: serial@f801c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
uart2: serial@f8024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
status = "okay";
};
flx0: flexcom@f8034000 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c2: i2c@600 {
compatible = "atmel,sama5d2-i2c";
reg = <0x600 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx0_clk>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
status = "okay";
};
};
shdwc@f8048010 {
atmel,shdwc-debouncer = <976>;
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};
watchdog@f8048040 {
status = "okay";
};
spi1: spi@fc000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
status = "okay";
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
at24@50 {
compatible = "24c02";
reg = <0x50>;
pagesize = <8>;
};
};
pinctrl@fc038000 {
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PA10__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led_gpio_default {
pinmux = <PIN_PB6__GPIO>,
<PIN_PB8__GPIO>,
<PIN_PB10__GPIO>;
bias-pull-up;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_nand_default: nand_default {
re_we_data {
pinmux = <PIN_PA22__D0>,
<PIN_PA23__D1>,
<PIN_PA24__D2>,
<PIN_PA25__D3>,
<PIN_PA26__D4>,
<PIN_PA27__D5>,
<PIN_PA28__D6>,
<PIN_PA29__D7>,
<PIN_PA30__NWE_NANDWE>,
<PIN_PB2__NRD_NANDOE>;
bias-pull-up;
};
ale_cle_rdy_cs {
pinmux = <PIN_PB0__A21_NANDALE>,
<PIN_PB1__A22_NANDCLE>,
<PIN_PC8__NANDRDY>,
<PIN_PA31__NCS3>;
bias-pull-up;
};
};
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
};
ck_cd_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>,
<PIN_PA17__SPI0_NPCS0>;
bias-disable;
};
pinctrl_spi1_default: spi1_default {
pinmux = <PIN_PC1__SPI1_SPCK>,
<PIN_PC2__SPI1_MOSI>,
<PIN_PC3__SPI1_MISO>,
<PIN_PC4__SPI1_NPCS0>;
bias-disable;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_uart2_default: uart2_default {
pinmux = <PIN_PD23__URXD2>,
<PIN_PD24__UTXD2>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB12__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PB11__GPIO>;
bias-disable;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
bp1 {
label = "PB_USER";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
red {
label = "red";
gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};

12
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -133,6 +133,18 @@
};
};
tcb0: timer@f800c000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
pdmic@f8018000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdmic_default>;

12
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -65,6 +65,18 @@
status = "okay";
};
tcb0: timer@f0010000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f0014000 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";

12
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
View File

@ -89,6 +89,18 @@
};
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

12
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View File

@ -130,6 +130,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

12
arch/arm/boot/dts/at91-sama5d4ek.dts
View File

@ -174,6 +174,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
watchdog@fc068640 {
status = "okay";
};

12
arch/arm/boot/dts/at91-vinco.dts
View File

@ -151,6 +151,18 @@
status = "okay";
};
tcb2: timer@fc024000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
macb1: ethernet@fc028000 {
phy-mode = "rmii";
status = "okay";

8
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -375,7 +375,9 @@
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
@ -385,7 +387,9 @@
};
tcb1: timer@fffa4000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa4000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0

12
arch/arm/boot/dts/at91rm9200ek.dts
View File

@ -32,6 +32,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffb0000 {
atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;

8
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -386,7 +386,9 @@
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
@ -396,7 +398,9 @@
};
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffdc000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0

12
arch/arm/boot/dts/at91sam9260ek.dts
View File

@ -69,6 +69,18 @@
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";

6
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -80,7 +80,7 @@
status = "disabled";
};
fb0: fb@0x00600000 {
fb0: fb@600000 {
compatible = "atmel,at91sam9261-lcdc";
reg = <0x00600000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
@ -125,7 +125,9 @@
ranges;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,

22
arch/arm/boot/dts/at91sam9261ek.dts
View File

@ -15,6 +15,14 @@
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
stdout-path = "serial0:115200n8";
clocksource {
timer = <&timer0>;
};
clockevent {
timer = <&timer1>;
};
};
memory {
@ -36,7 +44,7 @@
status = "okay";
};
fb0: fb@0x00600000 {
fb0: fb@600000 {
display = <&display0>;
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
status = "okay";
@ -125,6 +133,18 @@
};
apb {
tcb0: timer@fffa0000 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer1: timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
status = "okay";

6
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -389,7 +389,9 @@
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&slow_xtal>;
@ -999,7 +1001,7 @@
};
};
fb0: fb@0x00700000 {
fb0: fb@700000 {
compatible = "atmel,at91sam9263-lcdc";
reg = <0x00700000 0x1000>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;

14
arch/arm/boot/dts/at91sam9263ek.dts
View File

@ -37,6 +37,18 @@
status = "okay";
};
tcb0: timer@fff7c000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fff8c000 {
pinctrl-0 = <
&pinctrl_usart0
@ -95,7 +107,7 @@
};
};
fb0: fb@0x00700000 {
fb0: fb@700000 {
display = <&display0>;
status = "okay";

12
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -51,6 +51,18 @@
status = "okay";
};
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart0: serial@fffb0000 {
pinctrl-0 =
<&pinctrl_usart0

2
arch/arm/boot/dts/at91sam9g25ek.dts
View File

@ -25,7 +25,7 @@
};
i2c0: i2c@f8010000 {
ov2640: camera@0x30 {
ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";

10
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -415,7 +415,9 @@
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
@ -423,7 +425,9 @@
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
@ -1302,7 +1306,7 @@
};
};
fb0: fb@0x00500000 {
fb0: fb@500000 {
compatible = "atmel,at91sam9g45-lcdc";
reg = <0x00500000 0x1000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;

14
arch/arm/boot/dts/at91sam9m10g45ek.dts
View File

@ -39,6 +39,18 @@
status = "okay";
};
tcb0: timer@fff7c000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
usart1: serial@fff90000 {
pinctrl-0 =
<&pinctrl_usart1
@ -220,7 +232,7 @@
};
};
fb0: fb@0x00500000 {
fb0: fb@500000 {
display = <&display0>;
status = "okay";

8
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -446,7 +446,9 @@
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&clk32k>;
@ -454,7 +456,9 @@
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&clk32k>;

12
arch/arm/boot/dts/at91sam9n12ek.dts
View File

@ -42,6 +42,18 @@
status = "okay";
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f8010000 {
status = "okay";

4
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -124,7 +124,9 @@
ranges;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,

12
arch/arm/boot/dts/at91sam9rlek.dts
View File

@ -124,6 +124,18 @@
};
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
mmc0: mmc@fffa4000 {
pinctrl-0 = <
&pinctrl_board_mmc0

8
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -433,7 +433,9 @@
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;
@ -441,7 +443,9 @@
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;

12
arch/arm/boot/dts/at91sam9x5cm.dtsi
View File

@ -24,6 +24,18 @@
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
pinctrl@fffff400 {
1wire_cm {
pinctrl_1wire_cm: 1wire_cm-0 {

20
arch/arm/boot/dts/axp81x.dtsi
View File

@ -48,6 +48,22 @@
interrupt-controller;
#interrupt-cells = <1>;
axp_gpio: axp-gpio {
compatible = "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
pins = "GPIO1";
function = "ldo";
};
};
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
@ -113,11 +129,15 @@
};
reg_ldo_io0: ldo-io0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_ldo_io1: ldo-io1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};

4
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
View File

@ -10,12 +10,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

2
arch/arm/boot/dts/bcm2835-rpi-a.dts
View File

@ -10,7 +10,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

4
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
View File

@ -11,12 +11,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

2
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
View File

@ -11,7 +11,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

2
arch/arm/boot/dts/bcm2835-rpi-b.dts
View File

@ -11,7 +11,7 @@
leds {
act {
gpios = <&gpio 16 1>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
};

4
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@ -15,12 +15,12 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};

2
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@ -20,7 +20,7 @@
leds {
act {
gpios = <&gpio 47 0>;
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
};

Some files were not shown because too many files have changed in this diff Show More