forked from Minki/linux
clk: sunxi-ng: add support for the Allwinner H6 CCU
The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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@ -11,6 +11,11 @@ config SUN50I_A64_CCU
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN50I_H6_CCU
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bool "Support for the Allwinner H6 CCU"
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN4I_A10_CCU
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bool "Support for the Allwinner A10/A20 CCU"
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default MACH_SUN4I
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@ -22,6 +22,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
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# SoC support
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obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
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obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
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obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
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obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
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obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
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1207
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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1207
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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File diff suppressed because it is too large
Load Diff
56
drivers/clk/sunxi-ng/ccu-sun50i-h6.h
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56
drivers/clk/sunxi-ng/ccu-sun50i-h6.h
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@ -0,0 +1,56 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _CCU_SUN50I_H6_H_
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#define _CCU_SUN50I_H6_H_
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#define CLK_OSC12M 0
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#define CLK_PLL_CPUX 1
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#define CLK_PLL_DDR0 2
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 4
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#define CLK_PLL_PERIPH0_4X 5
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#define CLK_PLL_PERIPH1 6
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#define CLK_PLL_PERIPH1_2X 7
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#define CLK_PLL_PERIPH1_4X 8
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#define CLK_PLL_GPU 9
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#define CLK_PLL_VIDEO0 10
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#define CLK_PLL_VIDEO0_4X 11
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#define CLK_PLL_VIDEO1 12
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#define CLK_PLL_VIDEO1_4X 13
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#define CLK_PLL_VE 14
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#define CLK_PLL_DE 15
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#define CLK_PLL_HSIC 16
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#define CLK_PLL_AUDIO_BASE 17
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#define CLK_PLL_AUDIO 18
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#define CLK_PLL_AUDIO_2X 19
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#define CLK_PLL_AUDIO_4X 20
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/* CPUX clock exported for DVFS */
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#define CLK_AXI 22
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#define CLK_CPUX_APB 23
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#define CLK_PSI_AHB1_AHB2 24
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#define CLK_AHB3 25
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/* APB1 clock exported for PIO */
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#define CLK_APB2 27
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#define CLK_MBUS 28
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/* All module clocks and bus gates are exported except DRAM */
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#define CLK_DRAM 52
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#define CLK_BUS_DRAM 60
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#define CLK_NUMBER 137
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#endif /* _CCU_SUN50I_H6_H_ */
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124
include/dt-bindings/clock/sun50i-h6-ccu.h
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124
include/dt-bindings/clock/sun50i-h6-ccu.h
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@ -0,0 +1,124 @@
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define CLK_PLL_PERIPH0 3
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#define CLK_CPUX 21
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#define CLK_APB1 26
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#define CLK_DE 29
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#define CLK_BUS_DE 30
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#define CLK_DEINTERLACE 31
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#define CLK_BUS_DEINTERLACE 32
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#define CLK_GPU 33
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#define CLK_BUS_GPU 34
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#define CLK_CE 35
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#define CLK_BUS_CE 36
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#define CLK_VE 37
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#define CLK_BUS_VE 38
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#define CLK_EMCE 39
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#define CLK_BUS_EMCE 40
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#define CLK_VP9 41
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#define CLK_BUS_VP9 42
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#define CLK_BUS_DMA 43
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#define CLK_BUS_MSGBOX 44
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#define CLK_BUS_SPINLOCK 45
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#define CLK_BUS_HSTIMER 46
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#define CLK_AVS 47
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#define CLK_BUS_DBG 48
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#define CLK_BUS_PSI 49
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#define CLK_BUS_PWM 50
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#define CLK_BUS_IOMMU 51
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#define CLK_MBUS_DMA 53
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#define CLK_MBUS_VE 54
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#define CLK_MBUS_CE 55
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#define CLK_MBUS_TS 56
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#define CLK_MBUS_NAND 57
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#define CLK_MBUS_CSI 58
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#define CLK_MBUS_DEINTERLACE 59
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#define CLK_NAND0 61
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#define CLK_NAND1 62
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#define CLK_BUS_NAND 63
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#define CLK_MMC0 64
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#define CLK_MMC1 65
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#define CLK_MMC2 66
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#define CLK_BUS_MMC0 67
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#define CLK_BUS_MMC1 68
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#define CLK_BUS_MMC2 69
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#define CLK_BUS_UART0 70
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#define CLK_BUS_UART1 71
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#define CLK_BUS_UART2 72
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#define CLK_BUS_UART3 73
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#define CLK_BUS_I2C0 74
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#define CLK_BUS_I2C1 75
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#define CLK_BUS_I2C2 76
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#define CLK_BUS_I2C3 77
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#define CLK_BUS_SCR0 78
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#define CLK_BUS_SCR1 79
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#define CLK_SPI0 80
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#define CLK_SPI1 81
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#define CLK_BUS_SPI0 82
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#define CLK_BUS_SPI1 83
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#define CLK_BUS_EMAC 84
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#define CLK_TS 85
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#define CLK_BUS_TS 86
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#define CLK_IR_TX 87
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#define CLK_BUS_IR_TX 88
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#define CLK_BUS_THS 89
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#define CLK_I2S3 90
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#define CLK_I2S0 91
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#define CLK_I2S1 92
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#define CLK_I2S2 93
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#define CLK_BUS_I2S0 94
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#define CLK_BUS_I2S1 95
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#define CLK_BUS_I2S2 96
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#define CLK_BUS_I2S3 97
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#define CLK_SPDIF 98
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#define CLK_BUS_SPDIF 99
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#define CLK_DMIC 100
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#define CLK_BUS_DMIC 101
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#define CLK_AUDIO_HUB 102
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#define CLK_BUS_AUDIO_HUB 103
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#define CLK_USB_OHCI0 104
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#define CLK_USB_PHY0 105
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#define CLK_USB_PHY1 106
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#define CLK_USB_OHCI3 107
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#define CLK_USB_PHY3 108
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#define CLK_USB_HSIC_12M 109
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#define CLK_USB_HSIC 110
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#define CLK_BUS_OHCI0 111
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#define CLK_BUS_OHCI3 112
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#define CLK_BUS_EHCI0 113
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#define CLK_BUS_XHCI 114
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#define CLK_BUS_EHCI3 115
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#define CLK_BUS_OTG 116
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#define CLK_PCIE_REF_100M 117
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#define CLK_PCIE_REF 118
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#define CLK_PCIE_REF_OUT 119
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#define CLK_PCIE_MAXI 120
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#define CLK_PCIE_AUX 121
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#define CLK_BUS_PCIE 122
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#define CLK_HDMI 123
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#define CLK_HDMI_CEC 124
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#define CLK_BUS_HDMI 125
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#define CLK_BUS_TCON_TOP 126
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#define CLK_TCON_LCD0 127
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#define CLK_BUS_TCON_LCD0 128
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#define CLK_TCON_TV0 129
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#define CLK_BUS_TCON_TV0 130
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#define CLK_CSI_CCI 131
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#define CLK_CSI_TOP 132
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#define CLK_CSI_MCLK 133
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#define CLK_BUS_CSI 134
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#define CLK_HDCP 135
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#define CLK_BUS_HDCP 136
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
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include/dt-bindings/reset/sun50i-h6-ccu.h
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73
include/dt-bindings/reset/sun50i-h6-ccu.h
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
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#define _DT_BINDINGS_RESET_SUN50I_H6_H_
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#define RST_MBUS 0
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#define RST_BUS_DE 1
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#define RST_BUS_DEINTERLACE 2
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#define RST_BUS_GPU 3
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#define RST_BUS_CE 4
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#define RST_BUS_VE 5
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#define RST_BUS_EMCE 6
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#define RST_BUS_VP9 7
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#define RST_BUS_DMA 8
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#define RST_BUS_MSGBOX 9
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#define RST_BUS_SPINLOCK 10
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#define RST_BUS_HSTIMER 11
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#define RST_BUS_DBG 12
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#define RST_BUS_PSI 13
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#define RST_BUS_PWM 14
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#define RST_BUS_IOMMU 15
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#define RST_BUS_DRAM 16
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#define RST_BUS_NAND 17
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#define RST_BUS_MMC0 18
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#define RST_BUS_MMC1 19
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#define RST_BUS_MMC2 20
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#define RST_BUS_UART0 21
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#define RST_BUS_UART1 22
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#define RST_BUS_UART2 23
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#define RST_BUS_UART3 24
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#define RST_BUS_I2C0 25
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#define RST_BUS_I2C1 26
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#define RST_BUS_I2C2 27
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#define RST_BUS_I2C3 28
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#define RST_BUS_SCR0 29
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#define RST_BUS_SCR1 30
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#define RST_BUS_SPI0 31
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#define RST_BUS_SPI1 32
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#define RST_BUS_EMAC 33
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#define RST_BUS_TS 34
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#define RST_BUS_IR_TX 35
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#define RST_BUS_THS 36
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#define RST_BUS_I2S0 37
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#define RST_BUS_I2S1 38
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#define RST_BUS_I2S2 39
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#define RST_BUS_I2S3 40
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#define RST_BUS_SPDIF 41
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#define RST_BUS_DMIC 42
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#define RST_BUS_AUDIO_HUB 43
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#define RST_USB_PHY0 44
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#define RST_USB_PHY1 45
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#define RST_USB_PHY3 46
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#define RST_USB_HSIC 47
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#define RST_BUS_OHCI0 48
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#define RST_BUS_OHCI3 49
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#define RST_BUS_EHCI0 50
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#define RST_BUS_XHCI 51
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#define RST_BUS_EHCI3 52
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#define RST_BUS_OTG 53
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#define RST_BUS_PCIE 54
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#define RST_PCIE_POWERUP 55
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#define RST_BUS_HDMI 56
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#define RST_BUS_HDMI_SUB 57
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#define RST_BUS_TCON_TOP 58
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#define RST_BUS_TCON_LCD0 59
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#define RST_BUS_TCON_TV0 60
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#define RST_BUS_CSI 61
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#define RST_BUS_HDCP 62
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#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
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