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thunderbolt: Clarify register definitions for tb_cap_plug_events

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The USB4 1.0 specification outlines the `cap_plug_events` structure as
`VSC_CS_1`.  This shows that 4 bits of `VSC_CS_1` are TBT3 compatible in
USB4, but TBT3 controllers also support disabling XHCI.

Update the names and comments to more closely match the specification.
This should not change anything functionally.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Mario Limonciello 2022-03-03 07:13:27 -06:00 committed by Mika Westerberg
parent 6915812bbd
commit 51d4d64c7c
1 changed files with 11 additions and 7 deletions
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18
drivers/thunderbolt/tb_regs.h
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@ -146,14 +146,14 @@ struct tb_eeprom_ctl {
struct tb_cap_plug_events {
struct tb_cap_extended_short cap_header;
u32 __unknown1:2;
u32 plug_events:5;
u32 __unknown2:25;
u32 __unknown3;
u32 __unknown4;
u32 __unknown1:2; /* VSC_CS_1 */
u32 plug_events:5; /* VSC_CS_1 */
u32 __unknown2:25; /* VSC_CS_1 */
u32 vsc_cs_2;
u32 vsc_cs_3;
struct tb_eeprom_ctl eeprom_ctl;
u32 __unknown5[7];
u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
} __packed;
/* device headers */
@ -464,6 +464,10 @@ struct tb_regs_hop {
/* Plug Events registers */
#define TB_PLUG_EVENTS_USB_DISABLE BIT(2)
#define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3)
#define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4)
#define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5)
#define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6)
#define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b
#define TB_PLUG_EVENTS_PCIE_CMD 0x1c