forked from Minki/linux
PCI: Probe bridge window attributes once at enumeration-time
pci_bridge_check_ranges() determines whether a bridge supports the optional I/O and prefetchable memory windows and sets the flag bits in the bridge resources. This *could* be done once during enumeration except that the resource allocation code completely clears the flag bits, e.g., in the pci_assign_unassigned_bridge_resources() path. The problem with pci_bridge_check_ranges() in the resource allocation path is that we may allocate resources after devices have been claimed by drivers, and pci_bridge_check_ranges() *changes* the window registers to determine whether they're writable. This may break concurrent accesses to devices behind the bridge. Add a new pci_read_bridge_windows() to determine whether a bridge supports the optional windows, call it once during enumeration, remember the results, and change pci_bridge_check_ranges() so it doesn't touch the bridge windows but sets the flag bits based on those remembered results. Link: https://lore.kernel.org/linux-pci/1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com Link: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02082.html Reported-by: Yandong Xu <xuyandong2@huawei.com> Tested-by: Yandong Xu <xuyandong2@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Sagi Grimberg <sagi@grimberg.me> Cc: Ofer Hayut <ofer@lightbitslabs.com> Cc: Roy Shterman <roys@lightbitslabs.com> Cc: Keith Busch <keith.busch@intel.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
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@ -348,6 +348,57 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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}
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}
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static void pci_read_bridge_windows(struct pci_dev *bridge)
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{
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u16 io;
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u32 pmem, tmp;
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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if (!io) {
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pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
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}
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if (io)
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bridge->io_window = 1;
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/*
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* DECchip 21050 pass 2 errata: the bridge may miss an address
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* disconnect boundary by one PCI data phase. Workaround: do not
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* use prefetching on this device.
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*/
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if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
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return;
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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if (!pmem) {
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
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0xffe0fff0);
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
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}
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if (!pmem)
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return;
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bridge->pref_window = 1;
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if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
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/*
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* Bridge claims to have a 64-bit prefetchable memory
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* window; verify that the upper bits are actually
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* writable.
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*/
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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0xffffffff);
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
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if (tmp)
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bridge->pref_64_window = 1;
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}
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}
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static void pci_read_bridge_io(struct pci_bus *child)
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{
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struct pci_dev *dev = child->self;
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@ -1739,6 +1790,7 @@ int pci_setup_device(struct pci_dev *dev)
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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pci_read_bridge_windows(dev);
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set_pcie_hotplug_bridge(dev);
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pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
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if (pos) {
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@ -735,58 +735,21 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
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base/limit registers must be read-only and read as 0. */
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static void pci_bridge_check_ranges(struct pci_bus *bus)
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{
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u16 io;
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u32 pmem;
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struct pci_dev *bridge = bus->self;
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struct resource *b_res;
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struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
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b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
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b_res[1].flags |= IORESOURCE_MEM;
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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if (!io) {
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pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
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}
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if (io)
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if (bridge->io_window)
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b_res[0].flags |= IORESOURCE_IO;
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/* DECchip 21050 pass 2 errata: the bridge may miss an address
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disconnect boundary by one PCI data phase.
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Workaround: do not use prefetching on this device. */
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if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
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return;
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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if (!pmem) {
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
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0xffe0fff0);
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
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}
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if (pmem) {
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if (bridge->pref_window) {
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b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
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PCI_PREF_RANGE_TYPE_64) {
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if (bridge->pref_64_window) {
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b_res[2].flags |= IORESOURCE_MEM_64;
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b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
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}
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}
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/* double check if bridge does support 64 bit pref */
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if (b_res[2].flags & IORESOURCE_MEM_64) {
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u32 mem_base_hi, tmp;
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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&mem_base_hi);
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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0xffffffff);
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
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if (!tmp)
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b_res[2].flags &= ~IORESOURCE_MEM_64;
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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mem_base_hi);
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}
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}
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/* Helper function for sizing routines: find first available
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@ -373,6 +373,9 @@ struct pci_dev {
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bool match_driver; /* Skip attaching driver */
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unsigned int transparent:1; /* Subtractive decode bridge */
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unsigned int io_window:1; /* Bridge has I/O window */
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unsigned int pref_window:1; /* Bridge has pref mem window */
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unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
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unsigned int multifunction:1; /* Multi-function device */
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unsigned int is_busmaster:1; /* Is busmaster */
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