drm/amdgpu: add module parameter for async_gfx_ring enablement
0 means disable async_gfx_ring and is the default setting 1 means enable async_gfx_ring Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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				| @ -158,6 +158,7 @@ extern uint amdgpu_dm_abm_level; | ||||
| extern struct amdgpu_mgpu_info mgpu_info; | ||||
| extern int amdgpu_ras_enable; | ||||
| extern uint amdgpu_ras_mask; | ||||
| extern int amdgpu_async_gfx_ring; | ||||
| 
 | ||||
| #ifdef CONFIG_DRM_AMDGPU_SI | ||||
| extern int amdgpu_si_support; | ||||
|  | ||||
| @ -136,6 +136,7 @@ int amdgpu_emu_mode = 0; | ||||
| uint amdgpu_smu_memory_pool_size = 0; | ||||
| /* FBC (bit 0) disabled by default*/ | ||||
| uint amdgpu_dc_feature_mask = 0; | ||||
| int amdgpu_async_gfx_ring = 0; | ||||
| 
 | ||||
| struct amdgpu_mgpu_info mgpu_info = { | ||||
| 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), | ||||
| @ -565,6 +566,14 @@ MODULE_PARM_DESC(smu_memory_pool_size, | ||||
| 		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); | ||||
| module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); | ||||
| 
 | ||||
| /**
 | ||||
|  * DOC: async_gfx_ring (int) | ||||
|  * It is used to enable gfx rings that could be configured with different prioritites or equal priorities | ||||
|  */ | ||||
| MODULE_PARM_DESC(async_gfx_ring, | ||||
| 	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled (default), 1 = enabled)"); | ||||
| module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); | ||||
| 
 | ||||
| #ifdef CONFIG_HSA_AMD | ||||
| /**
 | ||||
|  * DOC: sched_policy (int) | ||||
|  | ||||
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