forked from Minki/linux
m32r: Simplify ei_handler code
Simplify and clean up messy ei_handler code in arch/m32r/kernel/entry.S. - Remove ifdef's for CONFIG_CHIP_* configulations. - Rearrange the M32700 workaround code. - Remove the messy platform-dependent interrupt check routines and consolidate them to common INT0/INT1/INT2 check routines for all platforms with cascaded interrupt controllers. Signed-off-by: Hitoshi Yamamoto <hitoshiy@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
This commit is contained in:
Hirokazu Takata
parent
e070fb743d
commit
5171b10051
@ -290,16 +290,12 @@ syscall_badsys:
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*/
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ENTRY(ei_handler)
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#if defined(CONFIG_CHIP_M32700)
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SWITCH_TO_KERNEL_STACK
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; WORKAROUND: force to clear SM bit and use the kernel stack (SPI).
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SWITCH_TO_KERNEL_STACK
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#endif
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SAVE_ALL
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mv r1, sp ; arg1(regs)
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#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
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|| defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
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|| defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
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; GET_ICU_STATUS;
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; GET_ICU_STATUS;
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seth r0, #shigh(M32R_ICU_ISTS_ADDR)
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ld r0, @(low(M32R_ICU_ISTS_ADDR),r0)
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push r0
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@ -314,10 +310,15 @@ ENTRY(ei_handler)
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;; IRQ exist check
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#if defined(CONFIG_CHIP_M32700)
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/* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
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beqz r0, 3f ; if (!irq_num) goto exit
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#else
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bnez r0, 0f
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ld24 r14, #0x00070000
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seth r0, #shigh(M32R_ICU_IMASK_ADDR)
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st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
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bra 1f
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.fillinsn
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0:
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#endif /* CONFIG_CHIP_M32700 */
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beqz r0, 1f ; if (!irq_num) goto exit
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#endif /* WORKAROUND */
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;; IPI check
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cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check
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bc 2f
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@ -333,218 +334,54 @@ ENTRY(ei_handler)
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1:
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addi sp, #4
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bra ret_to_intr
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#if defined(CONFIG_CHIP_M32700)
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/* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
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.fillinsn
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3:
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ld24 r14, #0x00070000
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seth r0, #shigh(M32R_ICU_IMASK_ADDR)
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st r14, @(low(M32R_ICU_IMASK_ADDR), r0)
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addi sp, #4
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bra ret_to_intr
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#endif /* WORKAROUND */
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;; do_IRQ
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.fillinsn
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2:
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srli r0, #2
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#if defined(CONFIG_PLAT_USRV)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, 9f
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(M32700UT_PLD_IRQ_BASE)
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.fillinsn
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9:
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#elif defined(CONFIG_PLAT_M32700UT)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, check_int0
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(M32700UT_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int0:
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add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
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bnez r2, check_int2
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; read ICU status of LAN-board
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seth r0, #high(M32700UT_LAN_ICUISTS)
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or3 r0, r0, #low(M32700UT_LAN_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int2:
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add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
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bnez r2, check_end
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; read ICU status of LCD-board
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seth r0, #high(M32700UT_LCD_ICUISTS)
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or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_end:
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#elif defined(CONFIG_PLAT_OPSPUT)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, check_int0
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(OPSPUT_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int0:
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add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
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bnez r2, check_int2
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; read ICU status of LAN-board
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seth r0, #high(OPSPUT_LAN_ICUISTS)
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or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int2:
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add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
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bnez r2, check_end
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; read ICU status of LCD-board
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seth r0, #high(OPSPUT_LCD_ICUISTS)
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or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_end:
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#endif /* CONFIG_PLAT_OPSPUT */
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bl do_IRQ ; r0(irq), r1(regs)
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#else /* not CONFIG_SMP */
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#else /* not CONFIG_SMP */
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srli r0, #22 ; r0(irq)
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#if defined(CONFIG_PLAT_USRV)
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#endif /* not CONFIG_SMP */
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#if defined(CONFIG_PLAT_HAS_INT1ICU)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, 1f
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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bnez r2, 3f
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seth r0, #shigh(M32R_INT1ICU_ISTS)
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lduh r0, @(low(M32R_INT1ICU_ISTS),r0) ; bit10-6 : ISN
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(M32700UT_PLD_IRQ_BASE)
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.fillinsn
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1:
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#elif defined(CONFIG_PLAT_M32700UT)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, check_int0
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(M32700UT_PLD_IRQ_BASE)
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addi r0, #(M32R_INT1ICU_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int0:
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add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
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bnez r2, check_int2
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; read ICU status of LAN-board
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seth r0, #high(M32700UT_LAN_ICUISTS)
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or3 r0, r0, #low(M32700UT_LAN_ICUISTS)
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lduh r0, @r0
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3:
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#endif /* CONFIG_PLAT_HAS_INT1ICU */
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#if defined(CONFIG_PLAT_HAS_INT0ICU)
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add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
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bnez r2, 4f
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seth r0, #shigh(M32R_INT0ICU_ISTS)
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lduh r0, @(low(M32R_INT0ICU_ISTS),r0) ; bit10-6 : ISN
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
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srli r0, #27 ; ISN
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addi r0, #(M32R_INT0ICU_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int2:
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add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
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bnez r2, check_end
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; read ICU status of LCD-board
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seth r0, #high(M32700UT_LCD_ICUISTS)
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or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
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lduh r0, @r0
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4:
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#endif /* CONFIG_PLAT_HAS_INT0ICU */
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#if defined(CONFIG_PLAT_HAS_INT2ICU)
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add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
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bnez r2, 5f
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seth r0, #shigh(M32R_INT2ICU_ISTS)
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lduh r0, @(low(M32R_INT2ICU_ISTS),r0) ; bit10-6 : ISN
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
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bra check_end
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srli r0, #27 ; ISN
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addi r0, #(M32R_INT2ICU_IRQ_BASE)
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; bra check_end
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.fillinsn
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5:
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#endif /* CONFIG_PLAT_HAS_INT2ICU */
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check_end:
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#elif defined(CONFIG_PLAT_OPSPUT)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, check_int0
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(OPSPUT_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int0:
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add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
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bnez r2, check_int2
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; read ICU status of LAN-board
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seth r0, #high(OPSPUT_LAN_ICUISTS)
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or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_int2:
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add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
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bnez r2, check_end
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; read ICU status of LCD-board
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seth r0, #high(OPSPUT_LCD_ICUISTS)
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or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_end:
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#elif defined(CONFIG_PLAT_M32104UT)
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add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
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bnez r2, check_end
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; read ICU status register of PLD
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seth r0, #high(PLD_ICUISTS)
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or3 r0, r0, #low(PLD_ICUISTS)
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lduh r0, @r0
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slli r0, #21
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srli r0, #27 ; ISN
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addi r0, #(M32104UT_PLD_IRQ_BASE)
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bra check_end
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.fillinsn
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check_end:
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#endif /* CONFIG_PLAT_M32104UT */
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bl do_IRQ
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#endif /* CONFIG_SMP */
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pop r14
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seth r0, #shigh(M32R_ICU_IMASK_ADDR)
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st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
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#else
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#error no chip configuration
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#endif
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ret_to_intr:
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bra ret_from_intr
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