forked from Minki/linux
drm/nv10/kms: add plane support for nv10-nv40
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
8aa816b0bb
commit
515de6b27f
@ -59,6 +59,7 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
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struct nv04_disp_priv *priv = (void *)subdev;
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u32 crtc0 = nv_rd32(priv, 0x600100);
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u32 crtc1 = nv_rd32(priv, 0x602100);
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u32 pvideo;
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if (crtc0 & 0x00000001) {
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nouveau_event_trigger(priv->base.vblank, 0);
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@ -69,6 +70,14 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
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nouveau_event_trigger(priv->base.vblank, 1);
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nv_wr32(priv, 0x602100, 0x00000001);
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}
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if (nv_device(priv)->chipset >= 0x10 &&
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nv_device(priv)->chipset <= 0x40) {
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pvideo = nv_rd32(priv, 0x8100);
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if (pvideo & ~0x11)
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nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
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nv_wr32(priv, 0x8100, pvideo);
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}
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}
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static int
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@ -33,6 +33,7 @@ nv04_mc_intr[] = {
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{ 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */
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{ 0x00000100, NVDEV_ENGINE_FIFO },
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{ 0x00001000, NVDEV_ENGINE_GR },
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{ 0x00010000, NVDEV_ENGINE_DISP },
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{ 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */
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{ 0x00100000, NVDEV_SUBDEV_TIMER },
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{ 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */
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@ -5,6 +5,7 @@ nouveau-y += dispnv04/dac.o
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nouveau-y += dispnv04/dfp.o
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nouveau-y += dispnv04/disp.o
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nouveau-y += dispnv04/hw.o
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nouveau-y += dispnv04/overlay.o
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nouveau-y += dispnv04/tvmodesnv17.o
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nouveau-y += dispnv04/tvnv04.o
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nouveau-y += dispnv04/tvnv17.o
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@ -140,6 +140,8 @@ nv04_display_create(struct drm_device *dev)
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func->save(encoder);
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}
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nouveau_overlay_init(dev);
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return 0;
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}
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@ -123,6 +123,9 @@ int nv04_tv_create(struct drm_connector *, struct dcb_output *);
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/* nv17_tv.c */
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int nv17_tv_create(struct drm_connector *, struct dcb_output *);
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/* overlay.c */
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void nouveau_overlay_init(struct drm_device *dev);
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static inline bool
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nv_two_heads(struct drm_device *dev)
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{
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@ -27,6 +27,7 @@
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#include "hw.h"
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#include <subdev/bios/pll.h>
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#include <subdev/fb.h>
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#include <subdev/clock.h>
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#include <subdev/timer.h>
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@ -664,6 +665,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_device *device = nv_device(drm->device);
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struct nouveau_timer *ptimer = nouveau_timer(device);
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struct nouveau_fb *pfb = nouveau_fb(device);
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struct nv04_crtc_reg *regp = &state->crtc_reg[head];
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uint32_t reg900;
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int i;
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@ -680,10 +682,10 @@ nv_load_state_ext(struct drm_device *dev, int head,
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nv_wr32(device, NV_PVIDEO_INTR_EN, 0);
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nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
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nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
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nv_wr32(device, NV_PVIDEO_LIMIT(0), 0); //drm->fb_available_size - 1);
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nv_wr32(device, NV_PVIDEO_LIMIT(1), 0); //drm->fb_available_size - 1);
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nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //drm->fb_available_size - 1);
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nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //drm->fb_available_size - 1);
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nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1);
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nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1);
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nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
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nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
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nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);
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NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
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320
drivers/gpu/drm/nouveau/dispnv04/overlay.c
Normal file
320
drivers/gpu/drm/nouveau/dispnv04/overlay.c
Normal file
@ -0,0 +1,320 @@
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/*
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* Copyright 2013 Ilia Mirkin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Implementation based on the pre-KMS implementation in xf86-video-nouveau,
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* written by Arthur Huillet.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fourcc.h>
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#include "nouveau_drm.h"
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#include "nouveau_bo.h"
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#include "nouveau_connector.h"
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#include "nouveau_display.h"
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#include "nvreg.h"
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struct nouveau_plane {
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struct drm_plane base;
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bool flip;
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struct nouveau_bo *cur;
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struct {
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struct drm_property *colorkey;
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struct drm_property *contrast;
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struct drm_property *brightness;
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struct drm_property *hue;
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struct drm_property *saturation;
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struct drm_property *iturbt_709;
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} props;
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int colorkey;
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int contrast;
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int brightness;
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int hue;
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int saturation;
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int iturbt_709;
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};
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static uint32_t formats[] = {
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DRM_FORMAT_NV12,
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DRM_FORMAT_UYVY,
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};
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/* Sine can be approximated with
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* http://en.wikipedia.org/wiki/Bhaskara_I's_sine_approximation_formula
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* sin(x degrees) ~= 4 x (180 - x) / (40500 - x (180 - x) )
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* Note that this only works for the range [0, 180].
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* Also note that sin(x) == -sin(x - 180)
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*/
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static inline int
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sin_mul(int degrees, int factor)
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{
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if (degrees > 180) {
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degrees -= 180;
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factor *= -1;
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}
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return factor * 4 * degrees * (180 - degrees) /
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(40500 - degrees * (180 - degrees));
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}
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/* cos(x) = sin(x + 90) */
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static inline int
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cos_mul(int degrees, int factor)
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{
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return sin_mul((degrees + 90) % 360, factor);
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}
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static int
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nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
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struct drm_framebuffer *fb, int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h)
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{
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struct nouveau_device *dev = nouveau_dev(plane->dev);
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struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
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struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nouveau_bo *cur = nv_plane->cur;
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bool flip = nv_plane->flip;
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int format = ALIGN(src_w * 4, 0x100);
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int soff = NV_PCRTC0_SIZE * nv_crtc->index;
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int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;
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int ret;
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if (format > 0xffff)
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return -EINVAL;
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ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM);
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if (ret)
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return ret;
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nv_plane->cur = nv_fb->nvbo;
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/* Source parameters given in 16.16 fixed point, ignore fractional. */
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src_x = src_x >> 16;
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src_y = src_y >> 16;
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src_w = src_w >> 16;
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src_h = src_h >> 16;
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nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
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nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
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nv_wr32(dev, NV_PVIDEO_BASE(flip), 0);
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nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);
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nv_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
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nv_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
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nv_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
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nv_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h);
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nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x);
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nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w);
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if (fb->pixel_format == DRM_FORMAT_NV12) {
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format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8;
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format |= NV_PVIDEO_FORMAT_PLANAR;
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}
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if (nv_plane->iturbt_709)
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format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709;
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if (nv_plane->colorkey & (1 << 24))
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format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY;
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if (fb->pixel_format == DRM_FORMAT_NV12) {
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nv_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
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nv_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
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nv_fb->nvbo->bo.offset + fb->offsets[1]);
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}
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nv_wr32(dev, NV_PVIDEO_FORMAT(flip), format);
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nv_wr32(dev, NV_PVIDEO_STOP, 0);
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/* TODO: wait for vblank? */
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nv_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1);
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nv_plane->flip = !flip;
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if (cur)
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nouveau_bo_unpin(cur);
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return 0;
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}
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static int
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nv10_disable_plane(struct drm_plane *plane)
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{
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struct nouveau_device *dev = nouveau_dev(plane->dev);
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struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
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nv_wr32(dev, NV_PVIDEO_STOP, 1);
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if (nv_plane->cur) {
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nouveau_bo_unpin(nv_plane->cur);
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nv_plane->cur = NULL;
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}
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return 0;
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}
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static void
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nv10_destroy_plane(struct drm_plane *plane)
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{
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nv10_disable_plane(plane);
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drm_plane_cleanup(plane);
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kfree(plane);
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}
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static void
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nv10_set_params(struct nouveau_plane *plane)
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{
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struct nouveau_device *dev = nouveau_dev(plane->base.dev);
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u32 luma = (plane->brightness - 512) << 16 | plane->contrast;
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u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) |
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(cos_mul(plane->hue, plane->saturation) & 0xffff);
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u32 format = 0;
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nv_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma);
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nv_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma);
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nv_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma);
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nv_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma);
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nv_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff);
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if (plane->cur) {
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if (plane->iturbt_709)
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format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709;
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if (plane->colorkey & (1 << 24))
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format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY;
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nv_mask(dev, NV_PVIDEO_FORMAT(plane->flip),
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NV_PVIDEO_FORMAT_MATRIX_ITURBT709 |
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NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY,
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format);
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}
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}
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static int
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nv10_set_property(struct drm_plane *plane,
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struct drm_property *property,
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uint64_t value)
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{
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struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
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if (property == nv_plane->props.colorkey)
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nv_plane->colorkey = value;
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else if (property == nv_plane->props.contrast)
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nv_plane->contrast = value;
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else if (property == nv_plane->props.brightness)
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nv_plane->brightness = value;
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else if (property == nv_plane->props.hue)
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nv_plane->hue = value;
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else if (property == nv_plane->props.saturation)
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nv_plane->saturation = value;
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else if (property == nv_plane->props.iturbt_709)
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nv_plane->iturbt_709 = value;
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else
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return -EINVAL;
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nv10_set_params(nv_plane);
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return 0;
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}
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static const struct drm_plane_funcs nv10_plane_funcs = {
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.update_plane = nv10_update_plane,
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.disable_plane = nv10_disable_plane,
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.set_property = nv10_set_property,
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.destroy = nv10_destroy_plane,
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};
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static void
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nv10_overlay_init(struct drm_device *device)
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{
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struct nouveau_device *dev = nouveau_dev(device);
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struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL);
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int ret;
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if (!plane)
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return;
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ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */,
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&nv10_plane_funcs,
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formats, ARRAY_SIZE(formats), false);
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if (ret)
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goto err;
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/* Set up the plane properties */
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plane->props.colorkey = drm_property_create_range(
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device, 0, "colorkey", 0, 0x01ffffff);
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plane->props.contrast = drm_property_create_range(
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device, 0, "contrast", 0, 8192 - 1);
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plane->props.brightness = drm_property_create_range(
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device, 0, "brightness", 0, 1024);
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plane->props.hue = drm_property_create_range(
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device, 0, "hue", 0, 359);
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plane->props.saturation = drm_property_create_range(
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device, 0, "saturation", 0, 8192 - 1);
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plane->props.iturbt_709 = drm_property_create_range(
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device, 0, "iturbt_709", 0, 1);
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if (!plane->props.colorkey ||
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!plane->props.contrast ||
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!plane->props.brightness ||
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!plane->props.hue ||
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!plane->props.saturation ||
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!plane->props.iturbt_709)
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goto cleanup;
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plane->colorkey = 0;
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drm_object_attach_property(&plane->base.base,
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plane->props.colorkey, plane->colorkey);
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plane->contrast = 0x1000;
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drm_object_attach_property(&plane->base.base,
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plane->props.contrast, plane->contrast);
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plane->brightness = 512;
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drm_object_attach_property(&plane->base.base,
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plane->props.brightness, plane->brightness);
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plane->hue = 0;
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drm_object_attach_property(&plane->base.base,
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plane->props.hue, plane->hue);
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plane->saturation = 0x1000;
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drm_object_attach_property(&plane->base.base,
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plane->props.saturation, plane->saturation);
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plane->iturbt_709 = 0;
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drm_object_attach_property(&plane->base.base,
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plane->props.iturbt_709, plane->iturbt_709);
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nv10_set_params(plane);
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nv_wr32(dev, NV_PVIDEO_STOP, 1);
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return;
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cleanup:
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drm_plane_cleanup(&plane->base);
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err:
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kfree(plane);
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nv_error(dev, "Failed to create plane\n");
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}
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void
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nouveau_overlay_init(struct drm_device *device)
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{
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struct nouveau_device *dev = nouveau_dev(device);
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if (dev->chipset >= 0x10 && dev->chipset <= 0x40)
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nv10_overlay_init(device);
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}
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