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drm/nouveau/ce: switch to instanced constructor

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-04 08:30:30 +10:00
parent b7da823a3e
commit 50551b15c7
22 changed files with 105 additions and 192 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb; struct notifier_block nb;
} acpi; } acpi;
struct nvkm_engine *ce[9];
struct nvkm_engine *cipher; struct nvkm_engine *cipher;
struct nvkm_disp *disp; struct nvkm_disp *disp;
struct nvkm_dma *dma; struct nvkm_dma *dma;
@ -121,7 +120,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
int (*ce[9] )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **); int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **);

9
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View File

@ -53,8 +53,13 @@ int nvkm_engine_ctor_(const struct nvkm_engine_func *, bool old, struct nvkm_dev
#define nvkm_engine_ctor_n(f,d,t,i,e,s) nvkm_engine_ctor_((f), false, (d), (t), (i), (e), (s)) #define nvkm_engine_ctor_n(f,d,t,i,e,s) nvkm_engine_ctor_((f), false, (d), (t), (i), (e), (s))
#define nvkm_engine_ctor__(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL #define nvkm_engine_ctor__(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define nvkm_engine_ctor(A...) nvkm_engine_ctor__(A, nvkm_engine_ctor_n, nvkm_engine_ctor_o)(A) #define nvkm_engine_ctor(A...) nvkm_engine_ctor__(A, nvkm_engine_ctor_n, nvkm_engine_ctor_o)(A)
int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *, int nvkm_engine_new__(const struct nvkm_engine_func *, bool old, struct nvkm_device *,
int index, bool enable, struct nvkm_engine **); enum nvkm_subdev_type, int, bool enable, struct nvkm_engine **);
#define nvkm_engine_new__o(f,d,i, e,s) nvkm_engine_new__((f), true, (d), (i), -1 , (e), (s))
#define nvkm_engine_new__n(f,d,t,i,e,s) nvkm_engine_new__((f), false, (d), (t), (i), (e), (s))
#define nvkm_engine_new___(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define nvkm_engine_new_(A...) nvkm_engine_new___(A, nvkm_engine_new__n, nvkm_engine_new__o)(A)
struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *); struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *);
void nvkm_engine_unref(struct nvkm_engine **); void nvkm_engine_unref(struct nvkm_engine **);
void nvkm_engine_tile(struct nvkm_engine *, int region); void nvkm_engine_tile(struct nvkm_engine *, int region);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -26,4 +26,5 @@ NVKM_LAYOUT_ONCE(NVKM_SUBDEV_CLK , struct nvkm_clk , clk)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp) NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp) NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp)
NVKM_LAYOUT_INST(NVKM_ENGINE_CE , struct nvkm_engine , ce, 9)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp) NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

18
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
View File

@ -3,13 +3,13 @@
#define __NVKM_CE_H__ #define __NVKM_CE_H__
#include <engine/falcon.h> #include <engine/falcon.h>
int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gt215_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gf100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gk104_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gm107_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gm107_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gm200_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gm200_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gp100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gp100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gp102_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gp102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gv100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int gv100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int tu102_ce_new(struct nvkm_device *, int, struct nvkm_engine **); int tu102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif #endif

8
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
View File

@ -63,8 +63,12 @@ void nvkm_falcon_del(struct nvkm_falcon **);
int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *); int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *);
void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *); void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *);
int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, int nvkm_falcon_new__(const struct nvkm_falcon_func *, bool old, struct nvkm_device *,
int index, bool enable, u32 addr, struct nvkm_engine **); enum nvkm_subdev_type, int inst, bool enable, u32 addr, struct nvkm_engine **);
#define nvkm_falcon_new__o(f,d,i, e,a,s) nvkm_falcon_new__((f), true, (d), (i), -1 , (e), (a), (s))
#define nvkm_falcon_new__n(f,d,t,i,e,a,s) nvkm_falcon_new__((f), false, (d), (t), (i), (e), (a), (s))
#define nvkm_falcon_new___(_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL
#define nvkm_falcon_new_(A...) nvkm_falcon_new___(A, nvkm_falcon_new__n, nvkm_falcon_new__o)(A)
struct nvkm_falcon_func { struct nvkm_falcon_func {
struct { struct {

6
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View File

@ -194,11 +194,11 @@ nvkm_engine_ctor_(const struct nvkm_engine_func *func, bool old, struct nvkm_dev
} }
int int
nvkm_engine_new_(const struct nvkm_engine_func *func, nvkm_engine_new__(const struct nvkm_engine_func *func, bool old, struct nvkm_device *device,
struct nvkm_device *device, int index, bool enable, enum nvkm_subdev_type type, int inst, bool enable,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
if (!(*pengine = kzalloc(sizeof(**pengine), GFP_KERNEL))) if (!(*pengine = kzalloc(sizeof(**pengine), GFP_KERNEL)))
return -ENOMEM; return -ENOMEM;
return nvkm_engine_ctor(func, device, index, enable, *pengine); return nvkm_engine_ctor_(func, old, device, type, inst, enable, *pengine);
} }

13
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,15 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h> #include <core/layout.h>
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
[NVKM_ENGINE_CE0 ] = "ce0",
[NVKM_ENGINE_CE1 ] = "ce1",
[NVKM_ENGINE_CE2 ] = "ce2",
[NVKM_ENGINE_CE3 ] = "ce3",
[NVKM_ENGINE_CE4 ] = "ce4",
[NVKM_ENGINE_CE5 ] = "ce5",
[NVKM_ENGINE_CE6 ] = "ce6",
[NVKM_ENGINE_CE7 ] = "ce7",
[NVKM_ENGINE_CE8 ] = "ce8",
[NVKM_ENGINE_CIPHER ] = "cipher", [NVKM_ENGINE_CIPHER ] = "cipher",
[NVKM_ENGINE_DISP ] = "disp", [NVKM_ENGINE_DISP ] = "disp",
[NVKM_ENGINE_DMAOBJ ] = "dma", [NVKM_ENGINE_DMAOBJ ] = "dma",
@ -211,10 +202,6 @@ nvkm_subdev_ctor_(const struct nvkm_subdev_func *func, bool old,
if (old) { if (old) {
switch (subdev->type) { switch (subdev->type) {
case NVKM_ENGINE_CE0 ... NVKM_ENGINE_CE_LAST:
subdev->type = NVKM_ENGINE_CE;
subdev->inst = subdev->index - NVKM_ENGINE_CE0;
break;
case NVKM_ENGINE_NVENC0 ... NVKM_ENGINE_NVENC_LAST: case NVKM_ENGINE_NVENC0 ... NVKM_ENGINE_NVENC_LAST:
subdev->type = NVKM_ENGINE_NVENC; subdev->type = NVKM_ENGINE_NVENC;
subdev->inst = subdev->index - NVKM_ENGINE_NVENC0; subdev->inst = subdev->index - NVKM_ENGINE_NVENC0;

13
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
View File

@ -63,16 +63,9 @@ gf100_ce1 = {
}; };
int int
gf100_ce_new(struct nvkm_device *device, int index, gf100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
if (index == NVKM_ENGINE_CE0) { return nvkm_falcon_new_(inst ? &gf100_ce1 : &gf100_ce0, device, type, inst, true,
return nvkm_falcon_new_(&gf100_ce0, device, index, true, 0x104000 + (inst * 0x1000), pengine);
0x104000, pengine);
} else
if (index == NVKM_ENGINE_CE1) {
return nvkm_falcon_new_(&gf100_ce1, device, index, true,
0x105000, pengine);
}
return -ENODEV;
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
View File

@ -94,8 +94,8 @@ gk104_ce = {
}; };
int int
gk104_ce_new(struct nvkm_device *device, int index, gk104_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gk104_ce, device, index, true, pengine); return nvkm_engine_new_(&gk104_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c
View File

@ -36,8 +36,8 @@ gm107_ce = {
}; };
int int
gm107_ce_new(struct nvkm_device *device, int index, gm107_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gm107_ce, device, index, true, pengine); return nvkm_engine_new_(&gm107_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c
View File

@ -35,8 +35,8 @@ gm200_ce = {
}; };
int int
gm200_ce_new(struct nvkm_device *device, int index, gm200_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gm200_ce, device, index, true, pengine); return nvkm_engine_new_(&gm200_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
View File

@ -95,8 +95,8 @@ gp100_ce = {
}; };
int int
gp100_ce_new(struct nvkm_device *device, int index, gp100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gp100_ce, device, index, true, pengine); return nvkm_engine_new_(&gp100_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c
View File

@ -37,8 +37,8 @@ gp102_ce = {
}; };
int int
gp102_ce_new(struct nvkm_device *device, int index, gp102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gp102_ce, device, index, true, pengine); return nvkm_engine_new_(&gp102_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
View File

@ -75,9 +75,9 @@ gt215_ce = {
}; };
int int
gt215_ce_new(struct nvkm_device *device, int index, gt215_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_falcon_new_(&gt215_ce, device, index, return nvkm_falcon_new_(&gt215_ce, device, type, inst,
(device->chipset != 0xaf), 0x104000, pengine); (device->chipset != 0xaf), 0x104000, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
View File

@ -33,8 +33,8 @@ gv100_ce = {
}; };
int int
gv100_ce_new(struct nvkm_device *device, int index, gv100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&gv100_ce, device, index, true, pengine); return nvkm_engine_new_(&gv100_ce, device, type, inst, true, pengine);
} }

4
drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
View File

@ -33,8 +33,8 @@ tu102_ce = {
}; };
int int
tu102_ce_new(struct nvkm_device *device, int index, tu102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
return nvkm_engine_new_(&tu102_ce, device, index, true, pengine); return nvkm_engine_new_(&tu102_ce, device, type, inst, true, pengine);
} }

174
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -1159,7 +1159,7 @@ nva3_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new }, .volt = { 0x00000001, nv40_volt_new },
.ce[0] = gt215_ce_new, .ce = { 0x00000001, gt215_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = nv50_dma_new, .dma = nv50_dma_new,
.fifo = g84_fifo_new, .fifo = g84_fifo_new,
@ -1193,7 +1193,7 @@ nva5_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new }, .volt = { 0x00000001, nv40_volt_new },
.ce[0] = gt215_ce_new, .ce = { 0x00000001, gt215_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = nv50_dma_new, .dma = nv50_dma_new,
.fifo = g84_fifo_new, .fifo = g84_fifo_new,
@ -1226,7 +1226,7 @@ nva8_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new }, .volt = { 0x00000001, nv40_volt_new },
.ce[0] = gt215_ce_new, .ce = { 0x00000001, gt215_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = nv50_dma_new, .dma = nv50_dma_new,
.fifo = g84_fifo_new, .fifo = g84_fifo_new,
@ -1323,7 +1323,7 @@ nvaf_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new }, .volt = { 0x00000001, nv40_volt_new },
.ce[0] = gt215_ce_new, .ce = { 0x00000001, gt215_ce_new },
.disp = mcp89_disp_new, .disp = mcp89_disp_new,
.dma = nv50_dma_new, .dma = nv50_dma_new,
.fifo = g84_fifo_new, .fifo = g84_fifo_new,
@ -1359,8 +1359,7 @@ nvc0_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000003, gf100_ce_new },
.ce[1] = gf100_ce_new,
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1396,7 +1395,7 @@ nvc1_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000001, gf100_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1432,7 +1431,7 @@ nvc3_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000001, gf100_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1468,8 +1467,7 @@ nvc4_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000003, gf100_ce_new },
.ce[1] = gf100_ce_new,
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1505,8 +1503,7 @@ nvc8_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000003, gf100_ce_new },
.ce[1] = gf100_ce_new,
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1542,8 +1539,7 @@ nvce_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000003, gf100_ce_new },
.ce[1] = gf100_ce_new,
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1579,7 +1575,7 @@ nvcf_chipset = {
.therm = { 0x00000001, gt215_therm_new }, .therm = { 0x00000001, gt215_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000001, gf100_ce_new },
.disp = gt215_disp_new, .disp = gt215_disp_new,
.dma = gf100_dma_new, .dma = gf100_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1614,7 +1610,7 @@ nvd7_chipset = {
.therm = { 0x00000001, gf119_therm_new }, .therm = { 0x00000001, gf119_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf117_volt_new }, .volt = { 0x00000001, gf117_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000001, gf100_ce_new },
.disp = gf119_disp_new, .disp = gf119_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1650,7 +1646,7 @@ nvd9_chipset = {
.therm = { 0x00000001, gf119_therm_new }, .therm = { 0x00000001, gf119_therm_new },
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, gf100_volt_new }, .volt = { 0x00000001, gf100_volt_new },
.ce[0] = gf100_ce_new, .ce = { 0x00000001, gf100_ce_new },
.disp = gf119_disp_new, .disp = gf119_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gf100_fifo_new, .fifo = gf100_fifo_new,
@ -1687,9 +1683,7 @@ nve4_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk104_disp_new, .disp = gk104_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk104_fifo_new, .fifo = gk104_fifo_new,
@ -1726,9 +1720,7 @@ nve6_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk104_disp_new, .disp = gk104_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk104_fifo_new, .fifo = gk104_fifo_new,
@ -1765,9 +1757,7 @@ nve7_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk104_disp_new, .disp = gk104_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk104_fifo_new, .fifo = gk104_fifo_new,
@ -1796,7 +1786,7 @@ nvea_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk20a_volt_new }, .volt = { 0x00000001, gk20a_volt_new },
.ce[2] = gk104_ce_new, .ce = { 0x00000004, gk104_ce_new },
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk20a_fifo_new, .fifo = gk20a_fifo_new,
.gr = gk20a_gr_new, .gr = gk20a_gr_new,
@ -1829,9 +1819,7 @@ nvf0_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk110_disp_new, .disp = gk110_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk110_fifo_new, .fifo = gk110_fifo_new,
@ -1867,9 +1855,7 @@ nvf1_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk110_disp_new, .disp = gk110_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk110_fifo_new, .fifo = gk110_fifo_new,
@ -1905,9 +1891,7 @@ nv106_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk110_disp_new, .disp = gk110_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk208_fifo_new, .fifo = gk208_fifo_new,
@ -1943,9 +1927,7 @@ nv108_chipset = {
.timer = { 0x00000001, nv41_timer_new }, .timer = { 0x00000001, nv41_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gk104_ce_new, .ce = { 0x00000007, gk104_ce_new },
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
.disp = gk110_disp_new, .disp = gk110_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gk208_fifo_new, .fifo = gk208_fifo_new,
@ -1981,8 +1963,7 @@ nv117_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gm107_ce_new, .ce = { 0x00000005, gm107_ce_new },
.ce[2] = gm107_ce_new,
.disp = gm107_disp_new, .disp = gm107_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm107_fifo_new, .fifo = gm107_fifo_new,
@ -2017,8 +1998,7 @@ nv118_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gm107_ce_new, .ce = { 0x00000005, gm107_ce_new },
.ce[2] = gm107_ce_new,
.disp = gm107_disp_new, .disp = gm107_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm107_fifo_new, .fifo = gm107_fifo_new,
@ -2051,9 +2031,7 @@ nv120_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gm200_ce_new, .ce = { 0x00000007, gm200_ce_new },
.ce[1] = gm200_ce_new,
.ce[2] = gm200_ce_new,
.disp = gm200_disp_new, .disp = gm200_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm200_fifo_new, .fifo = gm200_fifo_new,
@ -2089,9 +2067,7 @@ nv124_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gm200_ce_new, .ce = { 0x00000007, gm200_ce_new },
.ce[1] = gm200_ce_new,
.ce[2] = gm200_ce_new,
.disp = gm200_disp_new, .disp = gm200_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm200_fifo_new, .fifo = gm200_fifo_new,
@ -2127,9 +2103,7 @@ nv126_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk104_volt_new }, .volt = { 0x00000001, gk104_volt_new },
.ce[0] = gm200_ce_new, .ce = { 0x00000007, gm200_ce_new },
.ce[1] = gm200_ce_new,
.ce[2] = gm200_ce_new,
.disp = gm200_disp_new, .disp = gm200_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm200_fifo_new, .fifo = gm200_fifo_new,
@ -2157,7 +2131,7 @@ nv12b_chipset = {
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gm20b_volt_new }, .volt = { 0x00000001, gm20b_volt_new },
.ce[2] = gm200_ce_new, .ce = { 0x00000004, gm200_ce_new },
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gm20b_fifo_new, .fifo = gm20b_fifo_new,
.gr = gm20b_gr_new, .gr = gm20b_gr_new,
@ -2187,12 +2161,7 @@ nv130_chipset = {
.pmu = { 0x00000001, gm200_pmu_new }, .pmu = { 0x00000001, gm200_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp100_ce_new, .ce = { 0x0000003f, gp100_ce_new },
.ce[1] = gp100_ce_new,
.ce[2] = gp100_ce_new,
.ce[3] = gp100_ce_new,
.ce[4] = gp100_ce_new,
.ce[5] = gp100_ce_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.disp = gp100_disp_new, .disp = gp100_disp_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2227,10 +2196,7 @@ nv132_chipset = {
.pmu = { 0x00000001, gp102_pmu_new }, .pmu = { 0x00000001, gp102_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp102_ce_new, .ce = { 0x0000000f, gp102_ce_new },
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new, .disp = gp102_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2265,10 +2231,7 @@ nv134_chipset = {
.pmu = { 0x00000001, gp102_pmu_new }, .pmu = { 0x00000001, gp102_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp102_ce_new, .ce = { 0x0000000f, gp102_ce_new },
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new, .disp = gp102_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2303,10 +2266,7 @@ nv136_chipset = {
.pmu = { 0x00000001, gp102_pmu_new }, .pmu = { 0x00000001, gp102_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp102_ce_new, .ce = { 0x0000000f, gp102_ce_new },
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new, .disp = gp102_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2340,10 +2300,7 @@ nv137_chipset = {
.pmu = { 0x00000001, gp102_pmu_new }, .pmu = { 0x00000001, gp102_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp102_ce_new, .ce = { 0x0000000f, gp102_ce_new },
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new, .disp = gp102_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2378,10 +2335,7 @@ nv138_chipset = {
.pmu = { 0x00000001, gp102_pmu_new }, .pmu = { 0x00000001, gp102_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp102_ce_new, .ce = { 0x0000000f, gp102_ce_new },
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new, .disp = gp102_disp_new,
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
@ -2408,7 +2362,7 @@ nv13b_chipset = {
.pmu = { 0x00000001, gp10b_pmu_new }, .pmu = { 0x00000001, gp10b_pmu_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = gp100_ce_new, .ce = { 0x00000001, gp100_ce_new },
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp10b_fifo_new, .fifo = gp10b_fifo_new,
.gr = gp10b_gr_new, .gr = gp10b_gr_new,
@ -2439,16 +2393,8 @@ nv140_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce = { 0x000001ff, gv100_ce_new },
.disp = gv100_disp_new, .disp = gv100_disp_new,
.ce[0] = gv100_ce_new,
.ce[1] = gv100_ce_new,
.ce[2] = gv100_ce_new,
.ce[3] = gv100_ce_new,
.ce[4] = gv100_ce_new,
.ce[5] = gv100_ce_new,
.ce[6] = gv100_ce_new,
.ce[7] = gv100_ce_new,
.ce[8] = gv100_ce_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = gv100_fifo_new, .fifo = gv100_fifo_new,
.gr = gv100_gr_new, .gr = gv100_gr_new,
@ -2483,11 +2429,7 @@ nv162_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = tu102_ce_new, .ce = { 0x0000001f, tu102_ce_new },
.ce[1] = tu102_ce_new,
.ce[2] = tu102_ce_new,
.ce[3] = tu102_ce_new,
.ce[4] = tu102_ce_new,
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
@ -2521,11 +2463,7 @@ nv164_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = tu102_ce_new, .ce = { 0x0000001f, tu102_ce_new },
.ce[1] = tu102_ce_new,
.ce[2] = tu102_ce_new,
.ce[3] = tu102_ce_new,
.ce[4] = tu102_ce_new,
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
@ -2560,11 +2498,7 @@ nv166_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = tu102_ce_new, .ce = { 0x0000001f, tu102_ce_new },
.ce[1] = tu102_ce_new,
.ce[2] = tu102_ce_new,
.ce[3] = tu102_ce_new,
.ce[4] = tu102_ce_new,
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
@ -2600,11 +2534,7 @@ nv167_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = tu102_ce_new, .ce = { 0x0000001f, tu102_ce_new },
.ce[1] = tu102_ce_new,
.ce[2] = tu102_ce_new,
.ce[3] = tu102_ce_new,
.ce[4] = tu102_ce_new,
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
@ -2638,11 +2568,7 @@ nv168_chipset = {
.therm = { 0x00000001, gp100_therm_new }, .therm = { 0x00000001, gp100_therm_new },
.timer = { 0x00000001, gk20a_timer_new }, .timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new }, .top = { 0x00000001, gk104_top_new },
.ce[0] = tu102_ce_new, .ce = { 0x0000001f, tu102_ce_new },
.ce[1] = tu102_ce_new,
.ce[2] = tu102_ce_new,
.ce[3] = tu102_ce_new,
.ce[4] = tu102_ce_new,
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
@ -2938,7 +2864,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
struct nvkm_subdev *subdev; struct nvkm_subdev *subdev;
u64 mmio_base, mmio_size; u64 mmio_base, mmio_size;
u32 boot0, boot1, strap; u32 boot0, boot1, strap;
int ret = -EEXIST, i; int ret = -EEXIST, i, j;
unsigned chipset; unsigned chipset;
mutex_lock(&nv_devices_mutex); mutex_lock(&nv_devices_mutex);
@ -3248,15 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h> #include <core/layout.h>
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_CE0 , ce[0]);
_(NVKM_ENGINE_CE1 , ce[1]);
_(NVKM_ENGINE_CE2 , ce[2]);
_(NVKM_ENGINE_CE3 , ce[3]);
_(NVKM_ENGINE_CE4 , ce[4]);
_(NVKM_ENGINE_CE5 , ce[5]);
_(NVKM_ENGINE_CE6 , ce[6]);
_(NVKM_ENGINE_CE7 , ce[7]);
_(NVKM_ENGINE_CE8 , ce[8]);
_(NVKM_ENGINE_CIPHER , cipher); _(NVKM_ENGINE_CIPHER , cipher);
_(NVKM_ENGINE_DISP , disp); _(NVKM_ENGINE_DISP , disp);
_(NVKM_ENGINE_DMAOBJ , dma); _(NVKM_ENGINE_DMAOBJ , dma);
@ -3280,6 +3197,15 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
_(NVKM_ENGINE_SEC2 , sec2); _(NVKM_ENGINE_SEC2 , sec2);
_(NVKM_ENGINE_SW , sw); _(NVKM_ENGINE_SW , sw);
_(NVKM_ENGINE_VIC , vic); _(NVKM_ENGINE_VIC , vic);
case NVKM_ENGINE_CE1:
case NVKM_ENGINE_CE2:
case NVKM_ENGINE_CE3:
case NVKM_ENGINE_CE4:
case NVKM_ENGINE_CE5:
case NVKM_ENGINE_CE6:
case NVKM_ENGINE_CE7:
case NVKM_ENGINE_CE8:
break;
default: default:
WARN_ON(1); WARN_ON(1);
continue; continue;

9
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
View File

@ -335,9 +335,9 @@ nvkm_falcon = {
}; };
int int
nvkm_falcon_new_(const struct nvkm_falcon_func *func, nvkm_falcon_new__(const struct nvkm_falcon_func *func, bool old, struct nvkm_device *device,
struct nvkm_device *device, int index, bool enable, enum nvkm_subdev_type type, int inst, bool enable, u32 addr,
u32 addr, struct nvkm_engine **pengine) struct nvkm_engine **pengine)
{ {
struct nvkm_falcon *falcon; struct nvkm_falcon *falcon;
@ -351,6 +351,5 @@ nvkm_falcon_new_(const struct nvkm_falcon_func *func,
falcon->data.size = func->data.size; falcon->data.size = func->data.size;
*pengine = &falcon->engine; *pengine = &falcon->engine;
return nvkm_engine_ctor(&nvkm_falcon, device, index, return nvkm_engine_ctor_(&nvkm_falcon, old, device, type, inst, enable, &falcon->engine);
enable, &falcon->engine);
} }

4
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View File

@ -83,9 +83,9 @@ gf100_devinit_disable(struct nvkm_devinit *init)
if (r022500 & 0x00000008) if (r022500 & 0x00000008)
disable |= (1ULL << NVKM_ENGINE_MSENC); disable |= (1ULL << NVKM_ENGINE_MSENC);
if (r022500 & 0x00000100) if (r022500 & 0x00000100)
disable |= (1ULL << NVKM_ENGINE_CE0); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0);
if (r022500 & 0x00000200) if (r022500 & 0x00000200)
disable |= (1ULL << NVKM_ENGINE_CE1); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 1);
return disable; return disable;
} }

4
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
View File

@ -35,9 +35,9 @@ gm107_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0ULL; u64 disable = 0ULL;
if (r021c00 & 0x00000001) if (r021c00 & 0x00000001)
disable |= (1ULL << NVKM_ENGINE_CE0); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0);
if (r021c00 & 0x00000004) if (r021c00 & 0x00000004)
disable |= (1ULL << NVKM_ENGINE_CE2); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 2);
if (r021c04 & 0x00000001) if (r021c04 & 0x00000001)
disable |= (1ULL << NVKM_ENGINE_DISP); disable |= (1ULL << NVKM_ENGINE_DISP);

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View File

@ -80,7 +80,7 @@ gt215_devinit_disable(struct nvkm_devinit *init)
if (!(r00154c & 0x00000020)) if (!(r00154c & 0x00000020))
disable |= (1ULL << NVKM_ENGINE_MSVLD); disable |= (1ULL << NVKM_ENGINE_MSVLD);
if (!(r00154c & 0x00000200)) if (!(r00154c & 0x00000200))
disable |= (1ULL << NVKM_ENGINE_CE0); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0);
return disable; return disable;
} }

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View File

@ -46,7 +46,7 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
if (!(r00154c & 0x00000040)) if (!(r00154c & 0x00000040))
disable |= (1ULL << NVKM_ENGINE_VIC); disable |= (1ULL << NVKM_ENGINE_VIC);
if (!(r00154c & 0x00000200)) if (!(r00154c & 0x00000200))
disable |= (1ULL << NVKM_ENGINE_CE0); nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0);
return disable; return disable;
} }