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ASoC: da7219: Remove support for 32KHz PLL mode

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PLL mode based on 32KHz master clock not supported in
AB silicon so remove support from the driver.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Adam Thomson 2015-12-22 18:27:56 +00:00 committed by Mark Brown
parent 0aed64c176
commit 501f72e9c5
2 changed files with 2 additions and 10 deletions
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10
sound/soc/codecs/da7219.c
View File

@ -1074,11 +1074,8 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
u32 freq_ref; u32 freq_ref;
u64 frac_div; u64 frac_div;
/* Verify 32KHz, 2MHz - 54MHz MCLK provided, and set input divider */ /* Verify 2MHz - 54MHz MCLK provided, and set input divider */
if (da7219->mclk_rate == 32768) { if (da7219->mclk_rate < 2000000) {
indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
} else if (da7219->mclk_rate < 2000000) {
dev_err(codec->dev, "PLL input clock %d below valid range\n", dev_err(codec->dev, "PLL input clock %d below valid range\n",
da7219->mclk_rate); da7219->mclk_rate);
return -EINVAL; return -EINVAL;
@ -1119,9 +1116,6 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
case DA7219_SYSCLK_PLL_SRM: case DA7219_SYSCLK_PLL_SRM:
pll_ctrl |= DA7219_PLL_MODE_SRM; pll_ctrl |= DA7219_PLL_MODE_SRM;
break; break;
case DA7219_SYSCLK_PLL_32KHZ:
pll_ctrl |= DA7219_PLL_MODE_32KHZ;
break;
default: default:
dev_err(codec->dev, "Invalid PLL config\n"); dev_err(codec->dev, "Invalid PLL config\n");
return -EINVAL; return -EINVAL;

2
sound/soc/codecs/da7219.h
View File

@ -206,7 +206,6 @@
#define DA7219_PLL_MODE_BYPASS (0x0 << 6) #define DA7219_PLL_MODE_BYPASS (0x0 << 6)
#define DA7219_PLL_MODE_NORMAL (0x1 << 6) #define DA7219_PLL_MODE_NORMAL (0x1 << 6)
#define DA7219_PLL_MODE_SRM (0x2 << 6) #define DA7219_PLL_MODE_SRM (0x2 << 6)
#define DA7219_PLL_MODE_32KHZ (0x3 << 6)
/* DA7219_PLL_FRAC_TOP = 0x22 */ /* DA7219_PLL_FRAC_TOP = 0x22 */
#define DA7219_PLL_FBDIV_FRAC_TOP_SHIFT 0 #define DA7219_PLL_FBDIV_FRAC_TOP_SHIFT 0
@ -780,7 +779,6 @@ enum da7219_sys_clk {
DA7219_SYSCLK_MCLK = 0, DA7219_SYSCLK_MCLK = 0,
DA7219_SYSCLK_PLL, DA7219_SYSCLK_PLL,
DA7219_SYSCLK_PLL_SRM, DA7219_SYSCLK_PLL_SRM,
DA7219_SYSCLK_PLL_32KHZ
}; };
/* Regulators */ /* Regulators */