From 0458b88267c637fb872b0359da9ff0b243081e9e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 7 Dec 2020 20:05:14 +0100 Subject: [PATCH 01/20] soc: samsung: exynos-asv: don't defer early on not-supported SoCs Check if the SoC is really supported before gathering the needed resources. This fixes endless deferred probe on some SoCs other than Exynos5422 (like Exynos5410). Fixes: 5ea428595cc5 ("soc: samsung: Add Exynos Adaptive Supply Voltage driver") Cc: Signed-off-by: Marek Szyprowski Reviewed-by: Pankaj Dubey Link: https://lore.kernel.org/r/20201207190517.262051-2-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-asv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c index 8abf4dfaa5c5..f653e3533f0f 100644 --- a/drivers/soc/samsung/exynos-asv.c +++ b/drivers/soc/samsung/exynos-asv.c @@ -119,11 +119,6 @@ static int exynos_asv_probe(struct platform_device *pdev) u32 product_id = 0; int ret, i; - cpu_dev = get_cpu_device(0); - ret = dev_pm_opp_get_opp_count(cpu_dev); - if (ret < 0) - return -EPROBE_DEFER; - asv = devm_kzalloc(&pdev->dev, sizeof(*asv), GFP_KERNEL); if (!asv) return -ENOMEM; @@ -144,6 +139,11 @@ static int exynos_asv_probe(struct platform_device *pdev) return -ENODEV; } + cpu_dev = get_cpu_device(0); + ret = dev_pm_opp_get_opp_count(cpu_dev); + if (ret < 0) + return -EPROBE_DEFER; + ret = of_property_read_u32(pdev->dev.of_node, "samsung,asv-bin", &asv->of_bin); if (ret < 0) From 4561560dfb4f847a0b327d48bdd1f45bf1b6261f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Dec 2020 20:05:15 +0100 Subject: [PATCH 02/20] soc: samsung: exynos-asv: handle reading revision register error If regmap_read() fails, the product_id local variable will contain random value from the stack. Do not try to parse such value and fail the ASV driver probe. Fixes: 5ea428595cc5 ("soc: samsung: Add Exynos Adaptive Supply Voltage driver") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Pankaj Dubey Link: https://lore.kernel.org/r/20201207190517.262051-3-krzk@kernel.org --- drivers/soc/samsung/exynos-asv.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c index f653e3533f0f..5daeadc36382 100644 --- a/drivers/soc/samsung/exynos-asv.c +++ b/drivers/soc/samsung/exynos-asv.c @@ -129,7 +129,13 @@ static int exynos_asv_probe(struct platform_device *pdev) return PTR_ERR(asv->chipid_regmap); } - regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id); + ret = regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID, + &product_id); + if (ret < 0) { + dev_err(&pdev->dev, "Cannot read revision from ChipID: %d\n", + ret); + return -ENODEV; + } switch (product_id & EXYNOS_MASK) { case 0xE5422000: From 352bfbb3e0230c96b2bce00d2ac3f0de303cc7b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Dec 2020 19:54:57 +0100 Subject: [PATCH 03/20] soc: samsung: exynos-chipid: convert to driver and merge exynos-asv The Exynos Chip ID driver on Exynos SoCs has so far only informational purpose - to expose the SoC device in sysfs. No other drivers depend on it so there is really no benefit of initializing it early. The code would be the most flexible if converted to a regular driver. However there is already another driver - Exynos ASV (Adaptive Supply Voltage) - which binds to the device node of Chip ID. The solution is to convert the Exynos Chip ID to a built in driver and merge the Exynos ASV into it. This has several benefits: 1. Although the Exynos ASV driver binds to a device node present in all Exynos DTS (generic compatible), it fails to probe except on the supported ones (only Exynos5422). This means that the regular boot process has a planned/normal device probe failure. Merging the ASV into Chip ID will remove this probe failure because the final driver will always bind, just with disabled ASV features. 2. Allows to use dev_info() as the SoC bus is present (since core_initcall). 3. Could speed things up because of execution of Chip ID code in a SMP environment (after bringing up secondary CPUs, unlike early_initcall), This reduces the amount of work to be done early, when the kernel has to bring up critical devices. 5. Makes the Chip ID code defer-probe friendly, Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201207190517.262051-5-krzk@kernel.org Reviewed-by: Pankaj Dubey --- arch/arm/mach-exynos/Kconfig | 1 - drivers/soc/samsung/Kconfig | 12 +++-- drivers/soc/samsung/Makefile | 3 +- drivers/soc/samsung/exynos-asv.c | 45 +++++-------------- drivers/soc/samsung/exynos-asv.h | 2 + drivers/soc/samsung/exynos-chipid.c | 69 ++++++++++++++++++++--------- 6 files changed, 67 insertions(+), 65 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 56d272967fc0..5a48abac6af4 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS select ARM_GIC select EXYNOS_IRQ_COMBINER select COMMON_CLK_SAMSUNG - select EXYNOS_ASV select EXYNOS_CHIPID select EXYNOS_THERMAL select EXYNOS_PMU diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index fc7f48a92288..5745d7e5908e 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -7,21 +7,19 @@ menuconfig SOC_SAMSUNG if SOC_SAMSUNG -config EXYNOS_ASV - bool "Exynos Adaptive Supply Voltage support" if COMPILE_TEST - depends on (ARCH_EXYNOS && EXYNOS_CHIPID) || COMPILE_TEST - select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS - # There is no need to enable these drivers for ARMv8 config EXYNOS_ASV_ARM bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST - depends on EXYNOS_ASV + depends on EXYNOS_CHIPID config EXYNOS_CHIPID - bool "Exynos Chipid controller driver" if COMPILE_TEST + bool "Exynos ChipID controller and ASV driver" if COMPILE_TEST depends on ARCH_EXYNOS || COMPILE_TEST + select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS select MFD_SYSCON select SOC_BUS + help + Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. config EXYNOS_PMU bool "Exynos PMU controller driver" if COMPILE_TEST diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 59e8e9453f27..0c523a8de4eb 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -1,9 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_EXYNOS_ASV) += exynos-asv.o obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o -obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o +obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o exynos-asv.o obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c index 5daeadc36382..d60af8acc391 100644 --- a/drivers/soc/samsung/exynos-asv.c +++ b/drivers/soc/samsung/exynos-asv.c @@ -2,7 +2,9 @@ /* * Copyright (c) 2019 Samsung Electronics Co., Ltd. * http://www.samsung.com/ + * Copyright (c) 2020 Krzysztof Kozlowski * Author: Sylwester Nawrocki + * Author: Krzysztof Kozlowski * * Samsung Exynos SoC Adaptive Supply Voltage support */ @@ -10,12 +12,7 @@ #include #include #include -#include -#include -#include #include -#include -#include #include #include #include @@ -111,7 +108,7 @@ static int exynos_asv_update_opps(struct exynos_asv *asv) return 0; } -static int exynos_asv_probe(struct platform_device *pdev) +int exynos_asv_init(struct device *dev, struct regmap *regmap) { int (*probe_func)(struct exynos_asv *asv); struct exynos_asv *asv; @@ -119,21 +116,16 @@ static int exynos_asv_probe(struct platform_device *pdev) u32 product_id = 0; int ret, i; - asv = devm_kzalloc(&pdev->dev, sizeof(*asv), GFP_KERNEL); + asv = devm_kzalloc(dev, sizeof(*asv), GFP_KERNEL); if (!asv) return -ENOMEM; - asv->chipid_regmap = device_node_to_regmap(pdev->dev.of_node); - if (IS_ERR(asv->chipid_regmap)) { - dev_err(&pdev->dev, "Could not find syscon regmap\n"); - return PTR_ERR(asv->chipid_regmap); - } - + asv->chipid_regmap = regmap; + asv->dev = dev; ret = regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id); if (ret < 0) { - dev_err(&pdev->dev, "Cannot read revision from ChipID: %d\n", - ret); + dev_err(dev, "Cannot read revision from ChipID: %d\n", ret); return -ENODEV; } @@ -142,7 +134,9 @@ static int exynos_asv_probe(struct platform_device *pdev) probe_func = exynos5422_asv_init; break; default: - return -ENODEV; + dev_dbg(dev, "No ASV support for this SoC\n"); + devm_kfree(dev, asv); + return 0; } cpu_dev = get_cpu_device(0); @@ -150,14 +144,11 @@ static int exynos_asv_probe(struct platform_device *pdev) if (ret < 0) return -EPROBE_DEFER; - ret = of_property_read_u32(pdev->dev.of_node, "samsung,asv-bin", + ret = of_property_read_u32(dev->of_node, "samsung,asv-bin", &asv->of_bin); if (ret < 0) asv->of_bin = -EINVAL; - asv->dev = &pdev->dev; - dev_set_drvdata(&pdev->dev, asv); - for (i = 0; i < ARRAY_SIZE(asv->subsys); i++) asv->subsys[i].asv = asv; @@ -167,17 +158,3 @@ static int exynos_asv_probe(struct platform_device *pdev) return exynos_asv_update_opps(asv); } - -static const struct of_device_id exynos_asv_of_device_ids[] = { - { .compatible = "samsung,exynos4210-chipid" }, - {} -}; - -static struct platform_driver exynos_asv_driver = { - .driver = { - .name = "exynos-asv", - .of_match_table = exynos_asv_of_device_ids, - }, - .probe = exynos_asv_probe, -}; -module_platform_driver(exynos_asv_driver); diff --git a/drivers/soc/samsung/exynos-asv.h b/drivers/soc/samsung/exynos-asv.h index 3fd1f2acd999..dcbe154db31e 100644 --- a/drivers/soc/samsung/exynos-asv.h +++ b/drivers/soc/samsung/exynos-asv.h @@ -68,4 +68,6 @@ static inline u32 exynos_asv_opp_get_frequency(const struct exynos_asv_subsys *s return __asv_get_table_entry(&subsys->table, level, 0); } +int exynos_asv_init(struct device *dev, struct regmap *regmap); + #endif /* __LINUX_SOC_EXYNOS_ASV_H */ diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 1a76eade2ed6..fa6a9b9f6d70 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -2,20 +2,28 @@ /* * Copyright (c) 2019 Samsung Electronics Co., Ltd. * http://www.samsung.com/ + * Copyright (c) 2020 Krzysztof Kozlowski * * Exynos - CHIP ID support * Author: Pankaj Dubey * Author: Bartlomiej Zolnierkiewicz + * Author: Krzysztof Kozlowski + * + * Samsung Exynos SoC Adaptive Supply Voltage and Chip ID support */ -#include +#include +#include #include #include +#include #include #include #include #include +#include "exynos-asv.h" + static const struct exynos_soc_id { const char *name; unsigned int id; @@ -46,25 +54,17 @@ static const char * __init product_id_to_soc_id(unsigned int product_id) return NULL; } -static int __init exynos_chipid_early_init(void) +static int exynos_chipid_probe(struct platform_device *pdev) { struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; struct device_node *root; - struct device_node *syscon; struct regmap *regmap; u32 product_id; u32 revision; int ret; - syscon = of_find_compatible_node(NULL, NULL, - "samsung,exynos4210-chipid"); - if (!syscon) - return -ENODEV; - - regmap = device_node_to_regmap(syscon); - of_node_put(syscon); - + regmap = device_node_to_regmap(pdev->dev.of_node); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -74,7 +74,8 @@ static int __init exynos_chipid_early_init(void) revision = product_id & EXYNOS_REV_MASK; - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr), + GFP_KERNEL); if (!soc_dev_attr) return -ENOMEM; @@ -84,20 +85,24 @@ static int __init exynos_chipid_early_init(void) of_property_read_string(root, "model", &soc_dev_attr->machine); of_node_put(root); - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x", revision); + soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%x", revision); soc_dev_attr->soc_id = product_id_to_soc_id(product_id); if (!soc_dev_attr->soc_id) { pr_err("Unknown SoC\n"); - ret = -ENODEV; - goto err; + return -ENODEV; } /* please note that the actual registration will be deferred */ soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - ret = PTR_ERR(soc_dev); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + ret = exynos_asv_init(&pdev->dev, regmap); + if (ret) goto err; - } + + platform_set_drvdata(pdev, soc_dev); dev_info(soc_device_to_device(soc_dev), "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", @@ -106,9 +111,31 @@ static int __init exynos_chipid_early_init(void) return 0; err: - kfree(soc_dev_attr->revision); - kfree(soc_dev_attr); + soc_device_unregister(soc_dev); + return ret; } -arch_initcall(exynos_chipid_early_init); +static int exynos_chipid_remove(struct platform_device *pdev) +{ + struct soc_device *soc_dev = platform_get_drvdata(pdev); + + soc_device_unregister(soc_dev); + + return 0; +} + +static const struct of_device_id exynos_chipid_of_device_ids[] = { + { .compatible = "samsung,exynos4210-chipid" }, + {} +}; + +static struct platform_driver exynos_chipid_driver = { + .driver = { + .name = "exynos-chipid", + .of_match_table = exynos_chipid_of_device_ids, + }, + .probe = exynos_chipid_probe, + .remove = exynos_chipid_remove, +}; +builtin_platform_driver(exynos_chipid_driver); From c7e73b5051d672a707cc52195b761e2bc76dade0 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 9 Dec 2020 13:20:51 +0100 Subject: [PATCH 04/20] ARM: imx: mach-imx6ul: remove 14x14 EVK specific PHY fixup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove board specific PHY fixup introduced by commit: | 709bc0657fe6f9f5 ("ARM: imx6ul: add fec MAC refrence clock and phy fixup init") This fixup addresses boards with a specific configuration: a KSZ8081RNA PHY with attached clock source to XI (Pin 8) of the PHY equal to 50MHz. For the KSZ8081RND PHY, the meaning of the reg 0x1F bit 7 is different (compared to the KSZ8081RNA). A set bit means: - KSZ8081RNA: clock input to XI (Pin 8) is 50MHz for RMII - KSZ8081RND: clock input to XI (Pin 8) is 25MHz for RMII In other configurations, for example a KSZ8081RND PHY or a KSZ8081RNA with 25Mhz clock source, the PHY will glitch and stay in not recoverable state. It is not possible to detect the clock source frequency of the PHY. And it is not possible to automatically detect KSZ8081 PHY variant - both have same PHY ID. It is not possible to overwrite the fixup configuration by providing proper device tree description. The only way is to remove this fixup. If this patch breaks network functionality on your board, fix it by adding PHY node with following properties: ethernet-phy@x { ... micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; ... }; The board which was referred in the initial patch is already fixed. See: arch/arm/boot/dts/imx6ul-14x14-evk.dtsi Signed-off-by: Oleksij Rempel Reviewed-by: Fabio Estevam Tested-by: Sébastien Szymanski Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6ul.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index e018e716735f..eabcd35c01a5 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -27,30 +27,9 @@ static void __init imx6ul_enet_clk_init(void) pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n"); } -static int ksz8081_phy_fixup(struct phy_device *dev) -{ - if (dev && dev->interface == PHY_INTERFACE_MODE_MII) { - phy_write(dev, 0x1f, 0x8110); - phy_write(dev, 0x16, 0x201); - } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) { - phy_write(dev, 0x1f, 0x8190); - phy_write(dev, 0x16, 0x202); - } - - return 0; -} - -static void __init imx6ul_enet_phy_init(void) -{ - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, - ksz8081_phy_fixup); -} - static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); - imx6ul_enet_phy_init(); } static void __init imx6ul_init_machine(void) From fbaff050bb092836912b195459ca915b5fea8952 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Wed, 9 Dec 2020 18:20:23 +0100 Subject: [PATCH 05/20] ARM: mach-imx: imx6ul: Print SOC revision on boot Add the print of the CPU type and SOC revision during boot. Signed-off-by: Stefan Riedmueller Signed-off-by: Robert Karszniewicz Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6ul.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index eabcd35c01a5..35e81201cb5d 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -14,6 +14,7 @@ #include "common.h" #include "cpuidle.h" +#include "hardware.h" static void __init imx6ul_enet_clk_init(void) { @@ -34,6 +35,9 @@ static inline void imx6ul_enet_init(void) static void __init imx6ul_init_machine(void) { + imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL", + imx_get_soc_revision()); + of_platform_default_populate(NULL, NULL, NULL); imx6ul_enet_init(); imx_anatop_init(); From 6166174afc2bc74ca550af388508384b57d5163d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Jan 2021 18:44:40 +0100 Subject: [PATCH 06/20] soc: samsung: exynos-chipid: correct helpers __init annotation After converting to builtin driver, the probe function should not call __init functions anymore: >> WARNING: modpost: vmlinux.o(.text+0x8884d4): Section mismatch in reference from the function exynos_chipid_probe() to the function .init.text:product_id_to_soc_id() Reported-by: kernel test robot Fixes: 352bfbb3e023 ("soc: samsung: exynos-chipid: convert to driver and merge exynos-asv") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210105174440.120041-1-krzk@kernel.org --- drivers/soc/samsung/exynos-chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index fa6a9b9f6d70..5c1d0f97f766 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -44,7 +44,7 @@ static const struct exynos_soc_id { { "EXYNOS7420", 0xE7420000 }, }; -static const char * __init product_id_to_soc_id(unsigned int product_id) +static const char *product_id_to_soc_id(unsigned int product_id) { int i; From c09a3e6c97f00a525e23854d63f003aba9adfa41 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 13 Jan 2021 12:03:20 +0100 Subject: [PATCH 07/20] soc: samsung: pm_domains: Convert to regular platform driver When Exynos power domain driver was introduced, the only way to ensure that power domains will be instantiated before the devices which belongs to them was to initialize them early enough, before the devices are instantiated in the system. This in turn required not to use any platform device infrastructure at all, as there have been no way to ensure proper probe order between devices. This has been finally changed and upcomming patch "driver core: Set fw_devlink=on by default" ensures that each device will be probbed only when its resource providers are ready. This allows to convert Exynos power domain driver to regular platform driver. This is also required by the mentioned commit to enable probing any device which belongs to the Exynos power domains, as otherwise the core won't notice that the power domains are in fact available. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20210113110320.13149-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/pm_domains.c | 99 ++++++++++++++++---------------- 1 file changed, 49 insertions(+), 50 deletions(-) diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index ab8582971bfc..5ec0c13f0aaf 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ @@ -73,15 +73,15 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain) return exynos_pd_power(domain, false); } -static const struct exynos_pm_domain_config exynos4210_cfg __initconst = { +static const struct exynos_pm_domain_config exynos4210_cfg = { .local_pwr_cfg = 0x7, }; -static const struct exynos_pm_domain_config exynos5433_cfg __initconst = { +static const struct exynos_pm_domain_config exynos5433_cfg = { .local_pwr_cfg = 0xf, }; -static const struct of_device_id exynos_pm_domain_of_match[] __initconst = { +static const struct of_device_id exynos_pm_domain_of_match[] = { { .compatible = "samsung,exynos4210-pd", .data = &exynos4210_cfg, @@ -92,7 +92,7 @@ static const struct of_device_id exynos_pm_domain_of_match[] __initconst = { { }, }; -static __init const char *exynos_get_domain_name(struct device_node *node) +static const char *exynos_get_domain_name(struct device_node *node) { const char *name; @@ -101,60 +101,44 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } -static __init int exynos4_pm_init_power_domain(void) +static int exynos_pd_probe(struct platform_device *pdev) { - struct device_node *np; - const struct of_device_id *match; + const struct exynos_pm_domain_config *pm_domain_cfg; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct of_phandle_args child, parent; + struct exynos_pm_domain *pd; + int on, ret; - for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) { - const struct exynos_pm_domain_config *pm_domain_cfg; - struct exynos_pm_domain *pd; - int on; + pm_domain_cfg = of_device_get_match_data(dev); + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; - pm_domain_cfg = match->data; + pd->pd.name = exynos_get_domain_name(np); + if (!pd->pd.name) + return -ENOMEM; - pd = kzalloc(sizeof(*pd), GFP_KERNEL); - if (!pd) { - of_node_put(np); - return -ENOMEM; - } - pd->pd.name = exynos_get_domain_name(np); - if (!pd->pd.name) { - kfree(pd); - of_node_put(np); - return -ENOMEM; - } - - pd->base = of_iomap(np, 0); - if (!pd->base) { - pr_warn("%s: failed to map memory\n", __func__); - kfree_const(pd->pd.name); - kfree(pd); - continue; - } - - pd->pd.power_off = exynos_pd_power_off; - pd->pd.power_on = exynos_pd_power_on; - pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; - - on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; - - pm_genpd_init(&pd->pd, NULL, !on); - of_genpd_add_provider_simple(np, &pd->pd); + pd->base = of_iomap(np, 0); + if (!pd->base) { + kfree_const(pd->pd.name); + return -ENODEV; } - /* Assign the child power domains to their parents */ - for_each_matching_node(np, exynos_pm_domain_of_match) { - struct of_phandle_args child, parent; + pd->pd.power_off = exynos_pd_power_off; + pd->pd.power_on = exynos_pd_power_on; + pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; + on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; + + pm_genpd_init(&pd->pd, NULL, !on); + ret = of_genpd_add_provider_simple(np, &pd->pd); + + if (ret == 0 && of_parse_phandle_with_args(np, "power-domains", + "#power-domain-cells", 0, &parent) == 0) { child.np = np; child.args_count = 0; - if (of_parse_phandle_with_args(np, "power-domains", - "#power-domain-cells", 0, - &parent) != 0) - continue; - if (of_genpd_add_subdomain(&parent, &child)) pr_warn("%pOF failed to add subdomain: %pOF\n", parent.np, child.np); @@ -163,6 +147,21 @@ static __init int exynos4_pm_init_power_domain(void) parent.np, child.np); } - return 0; + pm_runtime_enable(dev); + return ret; +} + +static struct platform_driver exynos_pd_driver = { + .probe = exynos_pd_probe, + .driver = { + .name = "exynos-pd", + .of_match_table = exynos_pm_domain_of_match, + .suppress_bind_attrs = true, + } +}; + +static __init int exynos4_pm_init_power_domain(void) +{ + return platform_driver_register(&exynos_pd_driver); } core_initcall(exynos4_pm_init_power_domain); From 680ae44526ea9b656238ac768c8b6130961a0bdb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 12 Jan 2021 16:50:31 +0300 Subject: [PATCH 08/20] ARM: tegra: Don't enable unused PLLs on resume from suspend PLLC and PLLM are usually disabled on system suspend because all devices which use these PLLs are either suspended or switched away to other clock source. Don't enable unused PLLs on resume from suspend by keeping track of the enable-state of the PLLs across suspend-resume. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Tested-by: Matt Merhar Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra20.S | 38 ++++++++++-- arch/arm/mach-tegra/sleep-tegra30.S | 94 +++++++++++++++++++++++------ 2 files changed, 108 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 0e00ba8cf646..a5a36cce142a 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,11 +43,34 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -.macro pll_enable, rd, r_car_base, pll_base +#define PLLC_STORE_MASK (1 << 0) +#define PLLM_STORE_MASK (1 << 1) +#define PLLP_STORE_MASK (1 << 2) + +.macro test_pll_state, rd, test_mask + ldr \rd, tegra_pll_state + tst \rd, #\test_mask +.endm + +.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #\pll_mask + orrne \rd, \rd, #\pll_mask + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro pll_enable, rd, r_car_base, pll_base, test_mask + test_pll_state \rd, \test_mask + beq 1f + ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) orreq \rd, \rd, #(1 << 30) streq \rd, [\r_car_base, #\pll_base] +1: .endm .macro emc_device_mask, rd, base @@ -177,9 +200,9 @@ ENTRY(tegra20_lp1_reset) str r1, [r0, #CLK_RESET_CCLK_DIVIDER] str r1, [r0, #CLK_RESET_SCLK_DIVIDER] - pll_enable r1, r0, CLK_RESET_PLLM_BASE - pll_enable r1, r0, CLK_RESET_PLLP_BASE - pll_enable r1, r0, CLK_RESET_PLLC_BASE + pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK adr r2, tegra20_sdram_pad_address adr r4, tegra20_sdram_pad_save @@ -270,6 +293,10 @@ tegra20_switch_cpu_to_clk32k: add r1, r1, #2 wait_until r1, r7, r9 + store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + /* disable PLLM, PLLP and PLLC */ ldr r0, [r5, #CLK_RESET_PLLM_BASE] bic r0, r0, #(1 << 30) @@ -396,6 +423,9 @@ tegra20_sdram_pad_save: .long 0 .endr +tegra_pll_state: + .word 0x0 + .ltorg /* dummy symbol for end of IRAM */ .align L1_CACHE_SHIFT diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 2667bcdb5dc6..0cc40b6b2ba3 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -71,6 +71,13 @@ #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ +#define PLLA_STORE_MASK (1 << 0) +#define PLLC_STORE_MASK (1 << 1) +#define PLLM_STORE_MASK (1 << 2) +#define PLLP_STORE_MASK (1 << 3) +#define PLLX_STORE_MASK (1 << 4) +#define PLLM_PMC_STORE_MASK (1 << 5) + .macro emc_device_mask, rd, base ldr \rd, [\base, #EMC_ADR_CFG] tst \rd, #0x1 @@ -87,7 +94,43 @@ bne 1001b .endm -.macro pll_enable, rd, r_car_base, pll_base, pll_misc +.macro test_pll_state, rd, test_mask + ldr \rd, tegra_pll_state + tst \rd, #\test_mask +.endm + +.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #\pll_mask + orrne \rd, \rd, #\pll_mask + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro store_pllm_pmc_state, rd, tmp, pmc_base + ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] + tst \rd, #(1 << 12) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #PLLM_PMC_STORE_MASK + orrne \rd, \rd, #PLLM_PMC_STORE_MASK + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro pllm_pmc_enable, rd, pmc_base + test_pll_state \rd, PLLM_PMC_STORE_MASK + + ldrne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] + orrne \rd, \rd, #(1 << 12) + strne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] +.endm + +.macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask + test_pll_state \rd, \test_mask + beq 1f + ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) orreq \rd, \rd, #(1 << 30) @@ -102,13 +145,17 @@ orr \rd, \rd, #(1 << 18) str \rd, [\r_car_base, #\pll_misc] .endif +1: .endm -.macro pll_locked, rd, r_car_base, pll_base +.macro pll_locked, rd, r_car_base, pll_base, test_mask + test_pll_state \rd, \test_mask + beq 2f 1: ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 27) beq 1b +2: .endm .macro pll_iddq_exit, rd, car, iddq, iddq_bit @@ -342,34 +389,30 @@ ENTRY(tegra30_lp1_reset) /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE - ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] - orr r1, r1, #(1 << 12) - str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + pllm_pmc_enable r1, r2 - pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 - pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 - pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 + pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK b _pll_m_c_x_done _no_pll_iddq_exit: /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE - ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] - orr r1, r1, #(1 << 12) - str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + pllm_pmc_enable r1, r2 - pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC - pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC + pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK _pll_m_c_x_done: - pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC - pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC + pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK - pll_locked r1, r0, CLK_RESET_PLLM_BASE - pll_locked r1, r0, CLK_RESET_PLLP_BASE - pll_locked r1, r0, CLK_RESET_PLLA_BASE - pll_locked r1, r0, CLK_RESET_PLLC_BASE + pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK /* * CPUFreq driver could select other PLL for CPU. PLLX will be @@ -380,7 +423,7 @@ _pll_m_c_x_done: cmp r1, #TEGRA30 beq 1f - pll_locked r1, r0, CLK_RESET_PLLX_BASE + pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass @@ -593,6 +636,9 @@ tegra_sdram_pad_save: .long 0 .endr +tegra_pll_state: + .word 0x0 + /* * tegra30_tear_down_core * @@ -641,6 +687,14 @@ tegra30_switch_cpu_to_clk32k: add r1, r1, #2 wait_until r1, r7, r9 + /* store enable-state of PLLs */ + store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK + store_pllm_pmc_state r0, r1, r4 + /* disable PLLM via PMC in LP1 */ ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1 << 12) From d5d5b7f3e2ad4b7c7c80c6a4d5686fe8a9624947 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 20 Jan 2021 12:01:53 -0800 Subject: [PATCH 09/20] ARM: brcmstb: Add debug UART entry for 72116 72116 has the same memory map as 7255 and the same physical address for the UART, alias the definition accordingly. Reviewed-by: Linus Walleij Signed-off-by: Florian Fainelli --- arch/arm/include/debug/brcmstb.S | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 0ff32ffc610c..f684e3a815f6 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -25,6 +25,7 @@ #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) #define UARTA_3390 REG_PHYS_ADDR(0x40a900) +#define UARTA_72116 UARTA_7255 #define UARTA_7250 REG_PHYS_ADDR(0x40b400) #define UARTA_7255 REG_PHYS_ADDR(0x40c000) #define UARTA_7260 UARTA_7255 @@ -85,20 +86,21 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) -21: checkuart(\rp, \rv, 0x72160000, 7216) -22: checkuart(\rp, \rv, 0x07216400, 72164) -23: checkuart(\rp, \rv, 0x07216500, 72165) -24: checkuart(\rp, \rv, 0x72500000, 7250) -25: checkuart(\rp, \rv, 0x72550000, 7255) -26: checkuart(\rp, \rv, 0x72600000, 7260) -27: checkuart(\rp, \rv, 0x72680000, 7268) -28: checkuart(\rp, \rv, 0x72710000, 7271) -29: checkuart(\rp, \rv, 0x72780000, 7278) -30: checkuart(\rp, \rv, 0x73640000, 7364) -31: checkuart(\rp, \rv, 0x73660000, 7366) -32: checkuart(\rp, \rv, 0x07437100, 74371) -33: checkuart(\rp, \rv, 0x74390000, 7439) -34: checkuart(\rp, \rv, 0x74450000, 7445) +21: checkuart(\rp, \rv, 0x07211600, 72116) +22: checkuart(\rp, \rv, 0x72160000, 7216) +23: checkuart(\rp, \rv, 0x07216400, 72164) +24: checkuart(\rp, \rv, 0x07216500, 72165) +25: checkuart(\rp, \rv, 0x72500000, 7250) +26: checkuart(\rp, \rv, 0x72550000, 7255) +27: checkuart(\rp, \rv, 0x72600000, 7260) +28: checkuart(\rp, \rv, 0x72680000, 7268) +29: checkuart(\rp, \rv, 0x72710000, 7271) +30: checkuart(\rp, \rv, 0x72780000, 7278) +31: checkuart(\rp, \rv, 0x73640000, 7364) +32: checkuart(\rp, \rv, 0x73660000, 7366) +33: checkuart(\rp, \rv, 0x07437100, 74371) +34: checkuart(\rp, \rv, 0x74390000, 7439) +35: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 From 5674e314e674d5a7c4d38d8e9beed14b91ef04d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 11 Jan 2021 15:22:55 +0100 Subject: [PATCH 10/20] ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835 The BCM2711 has a number of instances of interrupt controllers handled by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). Let's select that driver as part of the ARCH_BCM2835 Kconfig option. Signed-off-by: Maxime Ripard Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20210111142309.193441-1-maxime@cerno.tech --- arch/arm/mach-bcm/Kconfig | 1 + arch/arm64/Kconfig.platforms | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 9b594ae98153..2890e61b2b46 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -161,6 +161,7 @@ config ARCH_BCM2835 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER + select BRCMSTB_L2_IRQ select PINCTRL select PINCTRL_BCM2835 select MFD_CORE diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6eecdef538bd..04c0c842c3e9 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -39,6 +39,7 @@ config ARCH_BCM2835 select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select BRCMSTB_L2_IRQ help This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. From 56d6fb12e64be09924a7140c43279583d49c4625 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 25 Jan 2021 15:26:06 +0100 Subject: [PATCH 11/20] soc: renesas: rcar-sysc: Use readl_poll_timeout_atomic() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the open-coded polling loops by calls to the readl_poll_timeout_atomic() helper macro. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20210125142606.1050130-1-geert+renesas@glider.be --- drivers/soc/renesas/rcar-sysc.c | 35 ++++++++++++++------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 9b235fc90027..d51ddc7d5232 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "rcar-sysc.h" @@ -44,13 +45,13 @@ #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */ -#define SYSCSR_RETRIES 100 +#define SYSCSR_TIMEOUT 100 #define SYSCSR_DELAY_US 1 #define PWRER_RETRIES 100 #define PWRER_DELAY_US 1 -#define SYSCISR_RETRIES 1000 +#define SYSCISR_TIMEOUT 1000 #define SYSCISR_DELAY_US 1 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */ @@ -68,7 +69,8 @@ static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val; static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) { unsigned int sr_bit, reg_offs; - int k; + u32 val; + int ret; if (on) { sr_bit = SYSCSR_PONENB; @@ -79,13 +81,10 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) } /* Wait until SYSC is ready to accept a power request */ - for (k = 0; k < SYSCSR_RETRIES; k++) { - if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit)) - break; - udelay(SYSCSR_DELAY_US); - } - - if (k == SYSCSR_RETRIES) + ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCSR, val, + val & BIT(sr_bit), SYSCSR_DELAY_US, + SYSCSR_TIMEOUT); + if (ret) return -EAGAIN; /* Submit power shutoff or power resume request */ @@ -99,10 +98,9 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) { unsigned int isr_mask = BIT(sysc_ch->isr_bit); unsigned int chan_mask = BIT(sysc_ch->chan_bit); - unsigned int status; + unsigned int status, k; unsigned long flags; - int ret = 0; - int k; + int ret; spin_lock_irqsave(&rcar_sysc_lock, flags); @@ -145,13 +143,10 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) } /* Wait until the power shutoff or resume request has completed * */ - for (k = 0; k < SYSCISR_RETRIES; k++) { - if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask) - break; - udelay(SYSCISR_DELAY_US); - } - - if (k == SYSCISR_RETRIES) + ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCISR, status, + status & isr_mask, SYSCISR_DELAY_US, + SYSCISR_TIMEOUT); + if (ret) ret = -EIO; iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); From 915769a8afd46d47e9501e2bf26fa86c1aec77a5 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 18 Dec 2020 12:54:11 +0200 Subject: [PATCH 12/20] MAINTAINERS: Update address for OMAP GPMC driver Updates my email address for OMAP GPMC driver. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 546aa66428c9..c36652aef387 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12894,7 +12894,7 @@ S: Orphan F: drivers/video/fbdev/omap/ OMAP GENERAL PURPOSE MEMORY CONTROLLER SUPPORT -M: Roger Quadros +M: Roger Quadros M: Tony Lindgren L: linux-omap@vger.kernel.org S: Maintained From 320f6f90cbe4818cf0d0f9441772d23aa441c506 Mon Sep 17 00:00:00 2001 From: Wang Qing Date: Thu, 17 Sep 2020 15:49:35 +0800 Subject: [PATCH 13/20] ARM: OMAP2+: fix spellint typo Change the comment typo: "ununsed" -> "unused". Signed-off-by: Wang Qing Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index dedd47e30b98..1feb0098705e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1299,7 +1299,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) * Due to a suspend or hibernation operation, the state of the registers * controlling this clkdm will be lost, save their context. */ -static int _clkdm_save_context(struct clockdomain *clkdm, void *ununsed) +static int _clkdm_save_context(struct clockdomain *clkdm, void *unused) { if (!arch_clkdm || !arch_clkdm->clkdm_save_context) return -EINVAL; @@ -1312,7 +1312,7 @@ static int _clkdm_save_context(struct clockdomain *clkdm, void *ununsed) * * Restore the register values for this clockdomain. */ -static int _clkdm_restore_context(struct clockdomain *clkdm, void *ununsed) +static int _clkdm_restore_context(struct clockdomain *clkdm, void *unused) { if (!arch_clkdm || !arch_clkdm->clkdm_restore_context) return -EINVAL; From 2dfc564bda4a31bc4439315448bd4da5182cb397 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Jan 2021 09:28:47 +0100 Subject: [PATCH 14/20] soc: renesas: rcar-sysc: Mark device node OF_POPULATED after init The R-Car System Controller (SYSC) driver registers PM domains from an early_initcall(). It does not use a platform driver, as secondary CPU startup on R-Car H1 needs to control the CPU power domains, before initialization of the driver framework. As fw_devlink only considers devices, it does not know that the System Controller is ready. Hence probing of on-chip devices that are part of the SYSC PM domain fails if fw_devlink is enabled: probe deferral - supplier e6180000.system-controller not ready Fix this by setting the OF_POPULATED flag for the SYSC device node after successful initialization. This will make of_link_to_phandle() ignore the SYSC device node as a dependency, and consumer devices will be probed again. Signed-off-by: Geert Uytterhoeven Reviewed-by: Saravana Kannan Link: https://lore.kernel.org/r/20210128082847.2205950-1-geert+renesas@glider.be --- drivers/soc/renesas/rcar-sysc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index d51ddc7d5232..53387a72ca00 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -434,6 +434,8 @@ static int __init rcar_sysc_pd_init(void) } error = of_genpd_add_provider_onecell(np, &domains->onecell_data); + if (!error) + of_node_set_flag(np, OF_POPULATED); out_put: of_node_put(np); From 579c6f925e5ae3a70ec32e936908066707dbfef5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Jan 2021 21:42:51 -0300 Subject: [PATCH 15/20] ARM: imx: Remove unused IMX_GPIO_NR() macro The IMX_GPIO_NR() macro was only used by non-DT i.MX platforms. As i.MX transitioned to a DT-only platform, get rid of this unused macro. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/hardware.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 7acf7ce467ed..0760fff39a0b 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -106,8 +106,4 @@ .type = _type, \ } -/* There's an off-by-one between the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ From 7f9942c61fa60eda7cc8e42f04bd25b7d175876e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 4 Feb 2021 17:23:42 +0100 Subject: [PATCH 16/20] ARM: s3c: fix fiq for clang IAS Building with the clang integrated assembler produces a couple of errors for the s3c24xx fiq support: arch/arm/mach-s3c/irq-s3c24xx-fiq.S:52:2: error: instruction 'subne' can not set flags, but 's' suffix specified subnes pc, lr, #4 @@ return, still have work to do arch/arm/mach-s3c/irq-s3c24xx-fiq.S:64:1: error: invalid symbol redefinition s3c24xx_spi_fiq_txrx: There are apparently two problems: one with extraneous or duplicate labels, and one with old-style opcode mnemonics. Stefan Agner has previously fixed other problems like this, but missed this particular file. Fixes: bec0806cfec6 ("spi_s3c24xx: add FIQ pseudo-DMA support") Cc: Stefan Agner Signed-off-by: Arnd Bergmann Reviewed-by: Nick Desaulniers Reviewed-by: Nathan Chancellor Link: https://lore.kernel.org/r/20210204162416.3030114-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/irq-s3c24xx-fiq.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S index b54cbd012241..5d238d9a798e 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S +++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S @@ -35,7 +35,6 @@ @ and an offset to the irq acknowledgment word ENTRY(s3c24xx_spi_fiq_rx) -s3c24xx_spi_fix_rx: .word fiq_rx_end - fiq_rx_start .word fiq_rx_irq_ack - fiq_rx_start fiq_rx_start: @@ -49,7 +48,7 @@ fiq_rx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do @@ set IRQ controller so that next op will trigger IRQ mov fiq_rtmp, #0 @@ -61,7 +60,6 @@ fiq_rx_irq_ack: fiq_rx_end: ENTRY(s3c24xx_spi_fiq_txrx) -s3c24xx_spi_fiq_txrx: .word fiq_txrx_end - fiq_txrx_start .word fiq_txrx_irq_ack - fiq_txrx_start fiq_txrx_start: @@ -76,7 +74,7 @@ fiq_txrx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do mov fiq_rtmp, #0 str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] @@ -88,7 +86,6 @@ fiq_txrx_irq_ack: fiq_txrx_end: ENTRY(s3c24xx_spi_fiq_tx) -s3c24xx_spi_fix_tx: .word fiq_tx_end - fiq_tx_start .word fiq_tx_irq_ack - fiq_tx_start fiq_tx_start: @@ -101,7 +98,7 @@ fiq_tx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do mov fiq_rtmp, #0 str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] From 49dc85ca3c78d938d9eb41e05efcd85c92626e84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 Feb 2021 14:36:14 +0100 Subject: [PATCH 17/20] ARM: s3c: irq-s3c24xx: include headers for missing declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include headers to fix W=1 build warnings: arch/arm/mach-s3c/irq-s3c24xx.c:389:5: warning: no previous prototype for ‘s3c24xx_set_fiq’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:683:13: warning: no previous prototype for ‘s3c2410_init_irq’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210206133615.119804-1-krzk@kernel.org --- arch/arm/mach-s3c/irq-s3c24xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 79b5f19af7a5..3368159d3f3e 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,7 @@ #include "cpu.h" #include "regs-irqtype.h" #include "pm.h" +#include "s3c24xx.h" #define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 From f503878564f5e68c1aeb1ea01e437060bf905c50 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 Feb 2021 14:36:15 +0100 Subject: [PATCH 18/20] ARM: s3c: irq-s3c24xx: staticize local functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make functions used only in this module static to fix W=1 build warnings: arch/arm/mach-s3c/irq-s3c24xx.c:360:39: warning: no previous prototype for ‘s3c24xx_handle_irq’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:1308:12: warning: no previous prototype for ‘s3c2410_init_intc_of’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:1330:12: warning: no previous prototype for ‘s3c2416_init_intc_of’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210206133615.119804-2-krzk@kernel.org --- arch/arm/mach-s3c/irq-s3c24xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3368159d3f3e..0c631c14a817 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -359,7 +359,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, return true; } -asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) +static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) { do { if (likely(s3c_intc[0])) @@ -1307,7 +1307,7 @@ static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { } }; -int __init s3c2410_init_intc_of(struct device_node *np, +static int __init s3c2410_init_intc_of(struct device_node *np, struct device_node *interrupt_parent) { return s3c_init_intc_of(np, interrupt_parent, @@ -1329,7 +1329,7 @@ static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { } }; -int __init s3c2416_init_intc_of(struct device_node *np, +static int __init s3c2416_init_intc_of(struct device_node *np, struct device_node *interrupt_parent) { return s3c_init_intc_of(np, interrupt_parent, From 24146a7d67ce0a37d044902e5fafc1aa5a6d98c8 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 5 Feb 2021 10:37:22 +0530 Subject: [PATCH 19/20] MAINTAINERS: Add linux-actions ML for Actions Semi Arch Add the linux-actions mailing list for the Actions Semi architecture. Signed-off-by: Cristian Ciocaltea Signed-off-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210205050722.8313-1-manivannan.sadhasivam@linaro.org' Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d9e8cef48552..ab761f089ca8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1512,6 +1512,7 @@ ARM/ACTIONS SEMI ARCHITECTURE M: Andreas Färber M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-actions@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/actions.yaml F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt From 36de760a5a90450bc1bd92b6938ce46f502da54d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 10 Feb 2021 18:23:03 +0100 Subject: [PATCH 20/20] MAINTAINERS: arm: samsung: include S3C headers in platform entry Several S3C24xx/S3C64xx headers in include/linux are not caught by Samsung S3C/S5P/Exynos maintainer entry and might look like abandoned. Include them in "ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" entry. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210210172303.335268-1-krzk@kernel.org' Signed-off-by: Arnd Bergmann --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ab761f089ca8..49f9346b2080 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2416,6 +2416,8 @@ F: drivers/*/*s5pv210* F: drivers/memory/samsung/ F: drivers/soc/samsung/ F: drivers/tty/serial/samsung* +F: include/linux/platform_data/*s3c* +F: include/linux/serial_s3c.h F: include/linux/soc/samsung/ N: exynos N: s3c2410