spi: dw: Discard dma_width member of the dw_spi structure
This member has exactly the same value as n_bytes of the DW SPI private data object, it's calculated at the same point of the transfer method, n_bytes isn't changed during the whole transfer, and they even serve for the same purpose - keep number of bytes per transfer word, though the dma_width is used only to calculate the DMA source/destination addresses width, which n_bytes could be also utilized for. Taking all of these into account let's replace the dma_width member usage with n_bytes one and remove the former. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200522000806.7381-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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@@ -133,10 +133,10 @@ static bool mid_spi_can_dma(struct spi_controller *master,
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return xfer->len > dws->fifo_len;
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return xfer->len > dws->fifo_len;
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}
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}
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static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
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static enum dma_slave_buswidth convert_dma_width(u8 n_bytes) {
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if (dma_width == 1)
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if (n_bytes == 1)
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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else if (dma_width == 2)
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else if (n_bytes == 2)
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return DMA_SLAVE_BUSWIDTH_2_BYTES;
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return DMA_SLAVE_BUSWIDTH_2_BYTES;
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return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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@@ -172,7 +172,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = 16;
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txconf.dst_maxburst = 16;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.dst_addr_width = convert_dma_width(dws->dma_width);
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txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
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txconf.device_fc = false;
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txconf.device_fc = false;
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dmaengine_slave_config(dws->txchan, &txconf);
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dmaengine_slave_config(dws->txchan, &txconf);
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@@ -221,7 +221,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = 16;
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rxconf.src_maxburst = 16;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.src_addr_width = convert_dma_width(dws->dma_width);
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rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
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rxconf.device_fc = false;
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rxconf.device_fc = false;
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dmaengine_slave_config(dws->rxchan, &rxconf);
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dmaengine_slave_config(dws->rxchan, &rxconf);
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@@ -353,7 +353,6 @@ static int dw_spi_transfer_one(struct spi_controller *master,
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}
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}
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dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
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dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
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dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
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cr0 = dws->update_cr0(master, spi, transfer);
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cr0 = dws->update_cr0(master, spi, transfer);
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dw_writel(dws, DW_SPI_CTRLR0, cr0);
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dw_writel(dws, DW_SPI_CTRLR0, cr0);
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@@ -136,7 +136,6 @@ struct dw_spi {
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void *rx_end;
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void *rx_end;
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int dma_mapped;
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int dma_mapped;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u8 n_bytes; /* current is a 1/2 bytes op */
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u32 dma_width;
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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u32 current_freq; /* frequency in hz */
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u32 current_freq; /* frequency in hz */
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