forked from Minki/linux
drm/mgag200: Move register initialization into separate function
Registers are initialized with constants. This is now done in mgag200_init_regs(), mgag200_set_dac_regs() and mgag200_set_pci_regs(). Later patches should move these calls from mode setting to device initialization. v2: * replace uint8_t with u8 Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Tested-by: John Donnelly <John.p.donnelly@oracle.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Emil Velikov <emil.velikov@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-12-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
parent
7fc1ae567d
commit
4f710d7ce8
@ -919,6 +919,152 @@ static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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return mga_crtc_do_set_base(mdev, fb, old_fb);
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}
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static void mgag200_set_pci_regs(struct mga_device *mdev)
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{
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uint32_t option = 0, option2 = 0;
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struct drm_device *dev = mdev->dev;
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switch (mdev->type) {
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case G200_SE_A:
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case G200_SE_B:
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if (mdev->has_sdram)
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option = 0x40049120;
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else
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option = 0x4004d120;
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option2 = 0x00008000;
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break;
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case G200_WB:
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case G200_EW3:
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option = 0x41049120;
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option2 = 0x0000b000;
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break;
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case G200_EV:
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option = 0x00000120;
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option2 = 0x0000b000;
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break;
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case G200_EH:
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case G200_EH3:
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option = 0x00000120;
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option2 = 0x0000b000;
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break;
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case G200_ER:
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break;
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}
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if (option)
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pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
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if (option2)
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pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
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}
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static void mgag200_set_dac_regs(struct mga_device *mdev)
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{
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size_t i;
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u8 dacvalue[] = {
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/* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
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/* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
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/* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
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/* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
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/* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
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/* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
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};
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switch (mdev->type) {
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case G200_SE_A:
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case G200_SE_B:
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dacvalue[MGA1064_VREF_CTL] = 0x03;
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dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
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MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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break;
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case G200_WB:
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case G200_EW3:
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dacvalue[MGA1064_VREF_CTL] = 0x07;
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break;
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case G200_EV:
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dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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break;
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case G200_EH:
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case G200_EH3:
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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break;
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case G200_ER:
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break;
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}
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for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
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if ((i <= 0x17) ||
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(i == 0x1b) ||
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(i == 0x1c) ||
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((i >= 0x1f) && (i <= 0x29)) ||
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((i >= 0x30) && (i <= 0x37)))
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continue;
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if (IS_G200_SE(mdev) &&
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((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
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continue;
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if ((mdev->type == G200_EV ||
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mdev->type == G200_WB ||
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mdev->type == G200_EH ||
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mdev->type == G200_EW3 ||
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mdev->type == G200_EH3) &&
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(i >= 0x44) && (i <= 0x4e))
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continue;
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WREG_DAC(i, dacvalue[i]);
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}
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if (mdev->type == G200_ER)
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WREG_DAC(0x90, 0);
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}
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static void mgag200_init_regs(struct mga_device *mdev)
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{
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u8 crtcext3, crtcext4, misc;
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mgag200_set_pci_regs(mdev);
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mgag200_set_dac_regs(mdev);
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WREG_SEQ(2, 0x0f);
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WREG_SEQ(3, 0x00);
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WREG_SEQ(4, 0x0e);
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WREG_CRT(10, 0);
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WREG_CRT(11, 0);
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WREG_CRT(12, 0);
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WREG_CRT(13, 0);
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WREG_CRT(14, 0);
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WREG_CRT(15, 0);
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RREG_ECRT(0x03, crtcext3);
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crtcext3 |= BIT(7); /* enable MGA mode */
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crtcext4 = 0x00;
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WREG_ECRT(0x03, crtcext3);
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WREG_ECRT(0x04, crtcext4);
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if (mdev->type == G200_ER)
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WREG_ECRT(0x24, 0x5);
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if (mdev->type == G200_EW3)
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WREG_ECRT(0x34, 0x5);
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misc = RREG8(MGA_MISC_IN);
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misc |= MGAREG_MISC_IOADSEL |
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MGAREG_MISC_RAMMAPEN |
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MGAREG_MISC_HIGH_PG_SEL;
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WREG8(MGA_MISC_OUT, misc);
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}
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static void mgag200_set_mode_regs(struct mga_device *mdev,
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const struct drm_display_mode *mode)
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{
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@ -1191,121 +1337,8 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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const struct drm_framebuffer *fb = crtc->primary->fb;
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int option = 0, option2 = 0;
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int i;
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unsigned char misc = 0;
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u8 crtcext3, crtcext4;
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static unsigned char dacvalue[] = {
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/* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
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/* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
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/* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
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/* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
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/* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
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/* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
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};
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switch (mdev->type) {
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case G200_SE_A:
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case G200_SE_B:
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dacvalue[MGA1064_VREF_CTL] = 0x03;
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dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
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MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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if (mdev->has_sdram)
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option = 0x40049120;
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else
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option = 0x4004d120;
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option2 = 0x00008000;
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break;
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case G200_WB:
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case G200_EW3:
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dacvalue[MGA1064_VREF_CTL] = 0x07;
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option = 0x41049120;
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option2 = 0x0000b000;
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break;
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case G200_EV:
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dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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option = 0x00000120;
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option2 = 0x0000b000;
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break;
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case G200_EH:
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case G200_EH3:
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dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
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MGA1064_MISC_CTL_DAC_RAM_CS;
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option = 0x00000120;
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option2 = 0x0000b000;
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break;
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case G200_ER:
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break;
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}
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for (i = 0; i < sizeof(dacvalue); i++) {
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if ((i <= 0x17) ||
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(i == 0x1b) ||
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(i == 0x1c) ||
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((i >= 0x1f) && (i <= 0x29)) ||
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((i >= 0x30) && (i <= 0x37)))
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continue;
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if (IS_G200_SE(mdev) &&
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((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
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continue;
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if ((mdev->type == G200_EV ||
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mdev->type == G200_WB ||
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mdev->type == G200_EH ||
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mdev->type == G200_EW3 ||
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mdev->type == G200_EH3) &&
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(i >= 0x44) && (i <= 0x4e))
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continue;
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WREG_DAC(i, dacvalue[i]);
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}
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if (mdev->type == G200_ER)
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WREG_DAC(0x90, 0);
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if (option)
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pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
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if (option2)
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pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
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WREG_SEQ(2, 0xf);
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WREG_SEQ(3, 0);
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WREG_SEQ(4, 0xe);
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WREG_CRT(10, 0);
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WREG_CRT(11, 0);
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WREG_CRT(12, 0);
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WREG_CRT(13, 0);
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WREG_CRT(14, 0);
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WREG_CRT(15, 0);
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RREG_ECRT(0x03, crtcext3);
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crtcext3 |= BIT(7); /* enable MGA mode */
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crtcext4 = 0x00;
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WREG_ECRT(0x03, crtcext3);
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WREG_ECRT(0x04, crtcext4);
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if (mdev->type == G200_ER)
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WREG_ECRT(0x24, 0x5);
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if (mdev->type == G200_EW3)
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WREG_ECRT(0x34, 0x5);
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misc = RREG8(MGA_MISC_IN);
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misc |= MGAREG_MISC_IOADSEL |
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MGAREG_MISC_RAMMAPEN |
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MGAREG_MISC_HIGH_PG_SEL;
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WREG8(MGA_MISC_OUT, misc);
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mgag200_init_regs(mdev);
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mgag200_set_format_regs(mdev, fb);
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mga_crtc_do_set_base(mdev, fb, old_fb);
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