drm/i915/gt: Expose engine properties via sysfs
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later we will add writeable sysadmin properties such
as per-engine timeout controls.
An example tree of the engine properties on Braswell:
/sys/class/drm/card0
└── engine
├── bcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── rcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── vcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
└── vecs0
├── capabilities
├── class
├── instance
├── known_capabilities
└── name
v2: Include stringified capabilities
v3: Include all known capabilities for futureproofing.
v4: Combine the two caps loops into one
v5: Hide underneath Kconfig.unstable for wider discussion
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Tested-by: Steve Carbonari <steven.carbonari@intel.com>
Reviewed-by: Steve Carbonari <steven.carbonari@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200228131716.3243616-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
efbf928824
commit
4ec76dbeb6
@ -109,7 +109,8 @@ gt-y += \
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gt/intel_rps.o \
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gt/intel_sseu.o \
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gt/intel_timeline.o \
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gt/intel_workarounds.o
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gt/intel_workarounds.o \
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gt/sysfs_engines.o
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# autogenerated null render state
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gt-y += \
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gt/gen6_renderstate.o \
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205
drivers/gpu/drm/i915/gt/sysfs_engines.c
Normal file
205
drivers/gpu/drm/i915/gt/sysfs_engines.c
Normal file
@ -0,0 +1,205 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/kobject.h>
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#include <linux/sysfs.h>
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#include "i915_drv.h"
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#include "intel_engine.h"
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#include "sysfs_engines.h"
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struct kobj_engine {
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struct kobject base;
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struct intel_engine_cs *engine;
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};
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static struct intel_engine_cs *kobj_to_engine(struct kobject *kobj)
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{
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return container_of(kobj, struct kobj_engine, base)->engine;
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}
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static ssize_t
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name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
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{
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return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
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}
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static struct kobj_attribute name_attr =
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__ATTR(name, 0444, name_show, NULL);
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static ssize_t
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class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
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{
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return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
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}
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static struct kobj_attribute class_attr =
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__ATTR(class, 0444, class_show, NULL);
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static ssize_t
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inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
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{
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return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
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}
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static struct kobj_attribute inst_attr =
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__ATTR(instance, 0444, inst_show, NULL);
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static const char * const vcs_caps[] = {
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[ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
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[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
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};
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static const char * const vecs_caps[] = {
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[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
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};
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static ssize_t repr_trim(char *buf, ssize_t len)
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{
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/* Trim off the trailing space and replace with a newline */
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if (len > PAGE_SIZE)
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len = PAGE_SIZE;
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if (len > 0)
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buf[len - 1] = '\n';
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return len;
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}
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static ssize_t
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__caps_show(struct intel_engine_cs *engine,
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u32 caps, char *buf, bool show_unknown)
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{
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const char * const *repr;
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int count, n;
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ssize_t len;
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BUILD_BUG_ON(!typecheck(typeof(caps), engine->uabi_capabilities));
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switch (engine->class) {
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case VIDEO_DECODE_CLASS:
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repr = vcs_caps;
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count = ARRAY_SIZE(vcs_caps);
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break;
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case VIDEO_ENHANCEMENT_CLASS:
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repr = vecs_caps;
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count = ARRAY_SIZE(vecs_caps);
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break;
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default:
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repr = NULL;
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count = 0;
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break;
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}
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GEM_BUG_ON(count > BITS_PER_TYPE(typeof(caps)));
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len = 0;
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for_each_set_bit(n,
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(unsigned long *)&caps,
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show_unknown ? BITS_PER_TYPE(typeof(caps)) : count) {
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if (n >= count || !repr[n]) {
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if (GEM_WARN_ON(show_unknown))
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len += snprintf(buf + len, PAGE_SIZE - len,
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"[%x] ", n);
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} else {
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len += snprintf(buf + len, PAGE_SIZE - len,
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"%s ", repr[n]);
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}
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if (GEM_WARN_ON(len >= PAGE_SIZE))
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break;
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}
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return repr_trim(buf, len);
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}
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static ssize_t
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caps_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
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{
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struct intel_engine_cs *engine = kobj_to_engine(kobj);
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return __caps_show(engine, engine->uabi_capabilities, buf, true);
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}
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static struct kobj_attribute caps_attr =
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__ATTR(capabilities, 0444, caps_show, NULL);
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static ssize_t
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all_caps_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
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{
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return __caps_show(kobj_to_engine(kobj), -1, buf, false);
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}
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static struct kobj_attribute all_caps_attr =
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__ATTR(known_capabilities, 0444, all_caps_show, NULL);
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static void kobj_engine_release(struct kobject *kobj)
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{
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kfree(kobj);
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}
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static struct kobj_type kobj_engine_type = {
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.release = kobj_engine_release,
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.sysfs_ops = &kobj_sysfs_ops
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};
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static struct kobject *
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kobj_engine(struct kobject *dir, struct intel_engine_cs *engine)
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{
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struct kobj_engine *ke;
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ke = kzalloc(sizeof(*ke), GFP_KERNEL);
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if (!ke)
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return NULL;
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kobject_init(&ke->base, &kobj_engine_type);
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ke->engine = engine;
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if (kobject_add(&ke->base, dir, "%s", engine->name)) {
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kobject_put(&ke->base);
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return NULL;
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}
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/* xfer ownership to sysfs tree */
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return &ke->base;
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}
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void intel_engines_add_sysfs(struct drm_i915_private *i915)
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{
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static const struct attribute *files[] = {
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&name_attr.attr,
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&class_attr.attr,
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&inst_attr.attr,
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&caps_attr.attr,
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&all_caps_attr.attr,
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NULL
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};
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struct device *kdev = i915->drm.primary->kdev;
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struct intel_engine_cs *engine;
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struct kobject *dir;
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dir = kobject_create_and_add("engine", &kdev->kobj);
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if (!dir)
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return;
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for_each_uabi_engine(engine, i915) {
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struct kobject *kobj;
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kobj = kobj_engine(dir, engine);
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if (!kobj)
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goto err_engine;
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if (sysfs_create_files(kobj, files))
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goto err_object;
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if (0) {
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err_object:
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kobject_put(kobj);
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err_engine:
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dev_err(kdev, "Failed to add sysfs engine '%s'\n",
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engine->name);
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break;
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}
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}
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}
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13
drivers/gpu/drm/i915/gt/sysfs_engines.h
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13
drivers/gpu/drm/i915/gt/sysfs_engines.h
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_ENGINE_SYSFS_H
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#define INTEL_ENGINE_SYSFS_H
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struct drm_i915_private;
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void intel_engines_add_sysfs(struct drm_i915_private *i915);
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#endif /* INTEL_ENGINE_SYSFS_H */
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@ -32,6 +32,7 @@
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#include "gt/intel_rc6.h"
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#include "gt/intel_rps.h"
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#include "gt/sysfs_engines.h"
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#include "i915_drv.h"
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#include "i915_sysfs.h"
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@ -606,6 +607,8 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
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drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
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i915_setup_error_capture(kdev);
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intel_engines_add_sysfs(dev_priv);
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}
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void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
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