leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/tilcdc: adding some more devicetree config

Browse Source 
Adding support for max-pixelclock and max-width device tree
entries. As some devices that use the tilcdc hardware module
have restrictions on the allowed/tested values.  Also update DT
bindings document to reflect new parameters.

Signed-off-by: Darren Etheridge <detheridge@ti.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Darren Etheridge 2013-06-21 13:52:23 -05:00 committed by Dave Airlie
parent 6bf02c66b9
commit 4e56434687
4 changed files with 65 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/drm/tilcdc/tilcdc.txt
View File

@ -10,6 +10,14 @@ Recommended properties:
services interrupts for this device.
- ti,hwmods: Name of the hwmod associated to the LCDC
Optional properties:
- max-bandwidth: The maximum pixels per second that the memory
interface / lcd controller combination can sustain
- max-width: The maximum horizontal pixel width supported by
the lcd controller.
- max-pixelclock: The maximum pixel clock that can be supported
by the lcd controller in KHz.
Example:
fb: fb@4830e000 {

23
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
View File

@ -443,10 +443,29 @@ int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
if (mode->vdisplay > 2048)
return MODE_VIRTUAL_Y;
/*
* some devices have a maximum allowed pixel clock
* configured from the DT
*/
if (mode->clock > priv->max_pixelclock) {
DBG("Pruning mode, pixel clock too high");
return MODE_CLOCK_HIGH;
}
/*
* some devices further limit the max horizontal resolution
* configured from the DT
*/
if (mode->hdisplay > priv->max_width)
return MODE_BAD_WIDTH;
/* filter out modes that would require too much memory bandwidth: */
bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode);
if (bandwidth > priv->max_bandwidth)
bandwidth = mode->hdisplay * mode->vdisplay *
drm_mode_vrefresh(mode);
if (bandwidth > priv->max_bandwidth) {
DBG("Pruning mode, exceeds defined bandwidth limit");
return MODE_BAD;
}
return MODE_OK;
}

15
drivers/gpu/drm/tilcdc/tilcdc_drv.c
View File

@ -212,7 +212,20 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
#endif
if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
priv->max_bandwidth = 1280 * 1024 * 60;
priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
if (of_property_read_u32(node, "ti,max-pixelclock",
&priv->max_pixelclock))
priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
pm_runtime_enable(dev->dev);

22
drivers/gpu/drm/tilcdc/tilcdc_drv.h
View File

@ -34,6 +34,18 @@
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
/* Defaulting to pixel clock defined on AM335x */
#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
/* Defaulting to max width as defined on AM335x */
#define TILCDC_DEFAULT_MAX_WIDTH 2048
/*
* This may need some tweaking, but want to allow at least 1280x1024@60
* with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
* be supportable
*/
#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
struct tilcdc_drm_private {
void __iomem *mmio;
@ -43,6 +55,16 @@ struct tilcdc_drm_private {
/* don't attempt resolutions w/ higher W * H * Hz: */
uint32_t max_bandwidth;
/*
* Pixel Clock will be restricted to some value as
* defined in the device datasheet measured in KHz
*/
uint32_t max_pixelclock;
/*
* Max allowable width is limited on a per device basis
* measured in pixels
*/
uint32_t max_width;
/* register contents saved across suspend/resume: */
u32 saved_register[12];