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Documentation: gpio: driver.rst: Fix warnings

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Fix warnings due to incorrect rst markup. Also improved the presentation
a little without changing the underlying content.

Signed-off-by: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
Link: https://lore.kernel.org/r/20191122034702.58563-1-dwlsalmeida@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Daniel W. S. Almeida 2019-11-22 00:47:02 -03:00 committed by Linus Walleij
parent 808b9931d5
commit 4e29b70d54
1 changed files with 12 additions and 9 deletions
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21
Documentation/driver-api/gpio/driver.rst
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@ -5,7 +5,7 @@ GPIO Driver Interface
This document serves as a guide for writers of GPIO chip drivers. This document serves as a guide for writers of GPIO chip drivers.
Each GPIO controller driver needs to include the following header, which defines Each GPIO controller driver needs to include the following header, which defines
the structures used to define a GPIO driver: the structures used to define a GPIO driver::
#include <linux/gpio/driver.h> #include <linux/gpio/driver.h>
@ -398,12 +398,15 @@ provided. A big portion of overhead code will be managed by gpiolib,
under the assumption that your interrupts are 1-to-1-mapped to the under the assumption that your interrupts are 1-to-1-mapped to the
GPIO line index: GPIO line index:
GPIO line offset Hardware IRQ .. csv-table::
0 0 :header: GPIO line offset, Hardware IRQ
1 1
2 2 0,0
... ... 1,1
ngpio-1 ngpio-1 2,2
...,...
ngpio-1, ngpio-1
If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask
and the flag need_valid_mask in gpio_irq_chip can be used to mask off some and the flag need_valid_mask in gpio_irq_chip can be used to mask off some
@ -413,7 +416,7 @@ The preferred way to set up the helpers is to fill in the
struct gpio_irq_chip inside struct gpio_chip before adding the gpio_chip. struct gpio_irq_chip inside struct gpio_chip before adding the gpio_chip.
If you do this, the additional irq_chip will be set up by gpiolib at the If you do this, the additional irq_chip will be set up by gpiolib at the
same time as setting up the rest of the GPIO functionality. The following same time as setting up the rest of the GPIO functionality. The following
is a typical example of a cascaded interrupt handler using gpio_irq_chip: is a typical example of a cascaded interrupt handler using gpio_irq_chip::
.. code-block:: c .. code-block:: c
@ -450,7 +453,7 @@ is a typical example of a cascaded interrupt handler using gpio_irq_chip:
return devm_gpiochip_add_data(dev, &g->gc, g); return devm_gpiochip_add_data(dev, &g->gc, g);
The helper support using hierarchical interrupt controllers as well. The helper support using hierarchical interrupt controllers as well.
In this case the typical set-up will look like this: In this case the typical set-up will look like this::
.. code-block:: c .. code-block:: c