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powerpc/perf: Add PPMU_ARCH_207S define

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Instead of separate bits for every POWER8 PMU feature, have a single one
for v2.07 of the architecture.

This saves us adding a MMCR2 define for a future patch.

Cc: stable@vger.kernel.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Joel Stanley 2014-07-08 16:08:21 +09:30 committed by Benjamin Herrenschmidt
parent f73128f4f6
commit 4d9690dd56
3 changed files with 5 additions and 6 deletions
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3
arch/powerpc/include/asm/perf_event_server.h
View File

@ -61,8 +61,7 @@ struct power_pmu {
#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */ #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */ #define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
#define PPMU_HAS_SIER 0x00000040 /* Has SIER */ #define PPMU_HAS_SIER 0x00000040 /* Has SIER */
#define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */ #define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
#define PPMU_EBB 0x00000100 /* supports event based branch */
/* /*
* Values for flags to get_alternatives() * Values for flags to get_alternatives()

6
arch/powerpc/perf/core-book3s.c
View File

@ -485,7 +485,7 @@ static bool is_ebb_event(struct perf_event *event)
* check that the PMU supports EBB, meaning those that don't can still * check that the PMU supports EBB, meaning those that don't can still
* use bit 63 of the event code for something else if they wish. * use bit 63 of the event code for something else if they wish.
*/ */
return (ppmu->flags & PPMU_EBB) && return (ppmu->flags & PPMU_ARCH_207S) &&
((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
} }
@ -777,7 +777,7 @@ void perf_event_print_debug(void)
if (ppmu->flags & PPMU_HAS_SIER) if (ppmu->flags & PPMU_HAS_SIER)
sier = mfspr(SPRN_SIER); sier = mfspr(SPRN_SIER);
if (ppmu->flags & PPMU_EBB) { if (ppmu->flags & PPMU_ARCH_207S) {
pr_info("MMCR2: %016lx EBBHR: %016lx\n", pr_info("MMCR2: %016lx EBBHR: %016lx\n",
mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
pr_info("EBBRR: %016lx BESCR: %016lx\n", pr_info("EBBRR: %016lx BESCR: %016lx\n",
@ -1696,7 +1696,7 @@ static int power_pmu_event_init(struct perf_event *event)
if (has_branch_stack(event)) { if (has_branch_stack(event)) {
/* PMU has BHRB enabled */ /* PMU has BHRB enabled */
if (!(ppmu->flags & PPMU_BHRB)) if (!(ppmu->flags & PPMU_ARCH_207S))
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }

2
arch/powerpc/perf/power8-pmu.c
View File

@ -792,7 +792,7 @@ static struct power_pmu power8_pmu = {
.get_constraint = power8_get_constraint, .get_constraint = power8_get_constraint,
.get_alternatives = power8_get_alternatives, .get_alternatives = power8_get_alternatives,
.disable_pmc = power8_disable_pmc, .disable_pmc = power8_disable_pmc,
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB, .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S,
.n_generic = ARRAY_SIZE(power8_generic_events), .n_generic = ARRAY_SIZE(power8_generic_events),
.generic_events = power8_generic_events, .generic_events = power8_generic_events,
.cache_events = &power8_cache_events, .cache_events = &power8_cache_events,