forked from Minki/linux
CLK: TI: APLL: add support for omap2 aplls
This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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aa76fcf473
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4d008589e2
@ -14,18 +14,32 @@ a subtype of a DPLL [2], although a simplified one at that.
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[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
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Required properties:
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- compatible : shall be "ti,dra7-apll-clock"
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- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
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- reg : address and length of the register set for controlling the APLL.
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It contains the information of registers in the following order:
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"control" - contains the control register base address
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"idlest" - contains the idlest register base address
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"control" - contains the control register offset
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"idlest" - contains the idlest register offset
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"autoidle" - contains the autoidle register offset (OMAP2 only)
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- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
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- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
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- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
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Examples:
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apll_pcie_ck: apll_pcie_ck@4a008200 {
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apll_pcie_ck: apll_pcie_ck {
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#clock-cells = <0>;
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clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
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reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
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reg = <0x021c>, <0x0220>;
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compatible = "ti,dra7-apll-clock";
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};
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apll96_ck: apll96_ck {
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#clock-cells = <0>;
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compatible = "ti,omap2-apll-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <2>;
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ti,idlest-shift = <8>;
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ti,clock-frequency = <96000000>;
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reg = <0x0500>, <0x0530>, <0x0520>;
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};
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@ -178,17 +178,6 @@ struct clksel {
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const struct clksel_rate *rates;
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};
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struct clk_hw_omap_ops {
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void (*find_idlest)(struct clk_hw_omap *oclk,
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void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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void (*find_companion)(struct clk_hw_omap *oclk,
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void __iomem **other_reg,
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u8 *other_bit);
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void (*allow_idle)(struct clk_hw_omap *oclk);
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void (*deny_idle)(struct clk_hw_omap *oclk);
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};
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unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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@ -221,3 +221,184 @@ cleanup:
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kfree(init);
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}
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CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
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#define OMAP2_EN_APLL_LOCKED 0x3
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#define OMAP2_EN_APLL_STOPPED 0x0
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static int omap2_apll_is_enabled(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct dpll_data *ad = clk->dpll_data;
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u32 v;
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v = ti_clk_ll_ops->clk_readl(ad->control_reg);
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v &= ad->enable_mask;
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v >>= __ffs(ad->enable_mask);
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return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
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}
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static unsigned long omap2_apll_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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if (omap2_apll_is_enabled(hw))
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return clk->fixed_rate;
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return 0;
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}
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static int omap2_apll_enable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct dpll_data *ad = clk->dpll_data;
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u32 v;
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int i = 0;
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v = ti_clk_ll_ops->clk_readl(ad->control_reg);
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v &= ~ad->enable_mask;
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v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
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ti_clk_ll_ops->clk_writel(v, ad->control_reg);
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while (1) {
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v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
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if (v & ad->idlest_mask)
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break;
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if (i > MAX_APLL_WAIT_TRIES)
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break;
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i++;
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udelay(1);
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}
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if (i == MAX_APLL_WAIT_TRIES) {
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pr_warn("%s failed to transition to locked\n",
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__clk_get_name(clk->hw.clk));
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return -EBUSY;
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}
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return 0;
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}
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static void omap2_apll_disable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct dpll_data *ad = clk->dpll_data;
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u32 v;
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v = ti_clk_ll_ops->clk_readl(ad->control_reg);
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v &= ~ad->enable_mask;
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v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
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ti_clk_ll_ops->clk_writel(v, ad->control_reg);
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}
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static struct clk_ops omap2_apll_ops = {
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.enable = &omap2_apll_enable,
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.disable = &omap2_apll_disable,
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.is_enabled = &omap2_apll_is_enabled,
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.recalc_rate = &omap2_apll_recalc,
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};
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static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
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{
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struct dpll_data *ad = clk->dpll_data;
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u32 v;
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v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg);
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v &= ~ad->autoidle_mask;
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v |= val << __ffs(ad->autoidle_mask);
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ti_clk_ll_ops->clk_writel(v, ad->control_reg);
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}
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#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
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#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
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static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
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{
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omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
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}
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static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
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{
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omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
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}
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static struct clk_hw_omap_ops omap2_apll_hwops = {
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.allow_idle = &omap2_apll_allow_idle,
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.deny_idle = &omap2_apll_deny_idle,
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};
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static void __init of_omap2_apll_setup(struct device_node *node)
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{
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struct dpll_data *ad = NULL;
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struct clk_hw_omap *clk_hw = NULL;
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struct clk_init_data *init = NULL;
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struct clk *clk;
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const char *parent_name;
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u32 val;
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ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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init = kzalloc(sizeof(*init), GFP_KERNEL);
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if (!ad || !clk_hw || !init)
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goto cleanup;
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clk_hw->dpll_data = ad;
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clk_hw->hw.init = init;
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init->ops = &omap2_apll_ops;
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init->name = node->name;
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clk_hw->ops = &omap2_apll_hwops;
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init->num_parents = of_clk_get_parent_count(node);
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if (init->num_parents != 1) {
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pr_err("%s must have one parent\n", node->name);
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goto cleanup;
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}
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parent_name = of_clk_get_parent_name(node, 0);
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init->parent_names = &parent_name;
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if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
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pr_err("%s missing clock-frequency\n", node->name);
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goto cleanup;
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}
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clk_hw->fixed_rate = val;
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if (of_property_read_u32(node, "ti,bit-shift", &val)) {
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pr_err("%s missing bit-shift\n", node->name);
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goto cleanup;
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}
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clk_hw->enable_bit = val;
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ad->enable_mask = 0x3 << val;
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ad->autoidle_mask = 0x3 << val;
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if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
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pr_err("%s missing idlest-shift\n", node->name);
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goto cleanup;
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}
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ad->idlest_mask = 1 << val;
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ad->control_reg = ti_clk_get_reg_addr(node, 0);
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ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
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ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
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if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
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goto cleanup;
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clk = clk_register(NULL, &clk_hw->hw);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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kfree(init);
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return;
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}
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cleanup:
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kfree(ad);
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kfree(clk_hw);
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kfree(init);
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}
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CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
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of_omap2_apll_setup);
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@ -94,7 +94,26 @@ struct dpll_data {
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u8 flags;
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};
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struct clk_hw_omap_ops;
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struct clk_hw_omap;
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/**
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* struct clk_hw_omap_ops - OMAP clk ops
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* @find_idlest: find idlest register information for a clock
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* @find_companion: find companion clock register information for a clock,
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* basically converts CM_ICLKEN* <-> CM_FCLKEN*
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* @allow_idle: enables autoidle hardware functionality for a clock
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* @deny_idle: prevent autoidle hardware functionality for a clock
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*/
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struct clk_hw_omap_ops {
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void (*find_idlest)(struct clk_hw_omap *oclk,
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void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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void (*find_companion)(struct clk_hw_omap *oclk,
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void __iomem **other_reg,
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u8 *other_bit);
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void (*allow_idle)(struct clk_hw_omap *oclk);
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void (*deny_idle)(struct clk_hw_omap *oclk);
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};
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/**
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* struct clk_hw_omap - OMAP struct clk
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