forked from Minki/linux
ARM: S5PC100: Modify SCLK_AUDIO{0,1,2} clock as sysclks
This patch modify SCLK_AUDIO{0,1,2} to be initial as sysclks on boot-time. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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068b432d74
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4cfd9c2530
@ -848,6 +848,18 @@ struct clksrc_sources clk_src_group3 = {
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.nr_sources = ARRAY_SIZE(clk_src_group3_list),
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};
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static struct clksrc_clk clk_sclk_audio0 = {
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.clk = {
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.name = "sclk_audio",
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.id = 0,
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.ctrlbit = (1 << 8),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group3,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
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};
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static struct clk *clk_src_group4_list[] = {
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[0] = &clk_mout_epll.clk,
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[1] = &clk_div_mpll.clk,
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@ -862,6 +874,18 @@ struct clksrc_sources clk_src_group4 = {
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.nr_sources = ARRAY_SIZE(clk_src_group4_list),
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};
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static struct clksrc_clk clk_sclk_audio1 = {
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.clk = {
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.name = "sclk_audio",
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.id = 1,
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.ctrlbit = (1 << 9),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group4,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
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};
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static struct clk *clk_src_group5_list[] = {
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[0] = &clk_mout_epll.clk,
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[1] = &clk_div_mpll.clk,
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@ -875,6 +899,18 @@ struct clksrc_sources clk_src_group5 = {
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.nr_sources = ARRAY_SIZE(clk_src_group5_list),
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};
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static struct clksrc_clk clk_sclk_audio2 = {
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.clk = {
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.name = "sclk_audio",
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.id = 2,
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.ctrlbit = (1 << 10),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group5,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
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};
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static struct clk *clk_src_group6_list[] = {
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[0] = &s5p_clk_27m,
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[1] = &clk_vclk54m,
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@ -999,39 +1035,6 @@ static struct clksrc_clk clksrcs[] = {
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},
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.sources = &clk_src_group6,
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.reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
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}, {
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.clk = {
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.name = "sclk_audio",
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.id = 0,
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.ctrlbit = (1 << 8),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group3,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_audio",
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.id = 1,
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.ctrlbit = (1 << 9),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group4,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_audio",
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.id = 2,
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.ctrlbit = (1 << 10),
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.enable = s5pc100_sclk1_ctrl,
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},
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.sources = &clk_src_group5,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_lcd",
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@ -1179,6 +1182,9 @@ static struct clksrc_clk *sysclks[] = {
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&clk_div_pclkd1,
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&clk_div_cam,
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&clk_div_hdmi,
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&clk_sclk_audio0,
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&clk_sclk_audio1,
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&clk_sclk_audio2,
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};
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void __init_or_cpufreq s5pc100_setup_clocks(void)
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