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drm/i915: Move engine reset preparation to i915_gem_reset_prepare()

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Now that we have prepare/finish routines for the GEM reset, move the
disabling of the engine->irq_tasklet into them to reduce repetition. The
device irq enable/disable is split out to ensure it is run first and
last always (even if the GPU reset fails).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484668747-9120-1-git-send-email-mika.kuoppala@intel.com
This commit is contained in:
Chris Wilson 2017-01-17 17:59:01 +02:00
parent 77affa3172
commit 4c96554365
2 changed files with 14 additions and 24 deletions
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21
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1728,22 +1728,6 @@ static int i915_resume_switcheroo(struct drm_device *dev)
return i915_drm_resume(dev); return i915_drm_resume(dev);
} }
static void disable_engines_irq(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
/* Ensure irq handler finishes, and not run again. */
disable_irq(dev_priv->drm.irq);
for_each_engine(engine, dev_priv, id)
tasklet_kill(&engine->irq_tasklet);
}
static void enable_engines_irq(struct drm_i915_private *dev_priv)
{
enable_irq(dev_priv->drm.irq);
}
/** /**
* i915_reset - reset chip after a hang * i915_reset - reset chip after a hang
* @dev_priv: device private to reset * @dev_priv: device private to reset
@ -1776,12 +1760,10 @@ void i915_reset(struct drm_i915_private *dev_priv)
error->reset_count++; error->reset_count++;
pr_notice("drm/i915: Resetting chip after gpu hang\n"); pr_notice("drm/i915: Resetting chip after gpu hang\n");
disable_irq(dev_priv->drm.irq);
i915_gem_reset_prepare(dev_priv); i915_gem_reset_prepare(dev_priv);
disable_engines_irq(dev_priv);
ret = intel_gpu_reset(dev_priv, ALL_ENGINES); ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
enable_engines_irq(dev_priv);
if (ret) { if (ret) {
if (ret != -ENODEV) if (ret != -ENODEV)
DRM_ERROR("Failed to reset chip: %i\n", ret); DRM_ERROR("Failed to reset chip: %i\n", ret);
@ -1816,6 +1798,7 @@ void i915_reset(struct drm_i915_private *dev_priv)
i915_queue_hangcheck(dev_priv); i915_queue_hangcheck(dev_priv);
wakeup: wakeup:
enable_irq(dev_priv->drm.irq);
wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS); wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
return; return;

17
drivers/gpu/drm/i915/i915_gem.c
View File

@ -2610,6 +2610,18 @@ i915_gem_find_active_request(struct intel_engine_cs *engine)
return NULL; return NULL;
} }
void i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
/* Ensure irq handler finishes, and not run again. */
for_each_engine(engine, dev_priv, id)
tasklet_kill(&engine->irq_tasklet);
i915_gem_revoke_fences(dev_priv);
}
static void reset_request(struct drm_i915_gem_request *request) static void reset_request(struct drm_i915_gem_request *request)
{ {
void *vaddr = request->ring->vaddr; void *vaddr = request->ring->vaddr;
@ -2629,11 +2641,6 @@ static void reset_request(struct drm_i915_gem_request *request)
dma_fence_set_error(&request->fence, -EIO); dma_fence_set_error(&request->fence, -EIO);
} }
void i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
{
i915_gem_revoke_fences(dev_priv);
}
static void i915_gem_reset_engine(struct intel_engine_cs *engine) static void i915_gem_reset_engine(struct intel_engine_cs *engine)
{ {
struct drm_i915_gem_request *request; struct drm_i915_gem_request *request;