forked from Minki/linux
dmaengine: ti: omap-dma: Add device tree match data and use it for cpu_pm
With old DMA code disabled for handling DMA requests for device tree based SoCs, we can move omap3 specific context save and restore to the dmaengine driver. Let's do this by adding cpu_pm notifier handling to save and restore context, and enable it based on device tree match data. This way we can use the match data later to configure more SoC specific features later on too. Note that we only clear the channels in use while the platform code also clears reserved channels 0 and 1 on high-security SoCs. Based on testing on n900, this is not needed though and the system idles just fine. With the dmaengine driver handling context save and restore, we must now remove the old custom calls for context save and restore. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Vinod Koul <vkoul@kernel.org> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
c6797bcde3
commit
4c74ecf792
@ -25,7 +25,6 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/omap-dma.h>
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#include <linux/omap-gpmc.h>
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#include <trace/events/power.h>
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@ -85,7 +84,6 @@ static void omap3_core_save_context(void)
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
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omap_dma_global_context_save();
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}
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static void omap3_core_restore_context(void)
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@ -96,7 +94,6 @@ static void omap3_core_restore_context(void)
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
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omap_dma_global_context_restore();
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}
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/*
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@ -547,9 +544,7 @@ int __init omap3_pm_init(void)
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local_irq_disable();
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omap_dma_global_context_save();
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omap3_save_secure_ram_context();
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omap_dma_global_context_restore();
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local_irq_enable();
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}
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@ -68,13 +68,6 @@ static void omap_clear_dma(int lch);
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static int enable_1510_mode;
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static u32 errata;
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static struct omap_dma_global_context_registers {
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u32 dma_irqenable_l0;
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u32 dma_irqenable_l1;
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u32 dma_ocp_sysconfig;
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u32 dma_gcr;
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} omap_dma_global_context;
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struct dma_link_info {
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int *linked_dmach_q;
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int no_of_lchs_linked;
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@ -905,42 +898,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
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#define omap1_dma_irq_handler NULL
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#endif
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/*
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* Note that we are currently using only IRQENABLE_L0 and L1.
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* As the DSP may be using IRQENABLE_L2 and L3, let's not
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* touch those for now.
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*/
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void omap_dma_global_context_save(void)
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{
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omap_dma_global_context.dma_irqenable_l0 =
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p->dma_read(IRQENABLE_L0, 0);
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omap_dma_global_context.dma_irqenable_l1 =
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p->dma_read(IRQENABLE_L1, 0);
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omap_dma_global_context.dma_ocp_sysconfig =
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p->dma_read(OCP_SYSCONFIG, 0);
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omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
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}
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void omap_dma_global_context_restore(void)
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{
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int ch;
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p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
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p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
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OCP_SYSCONFIG, 0);
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p->dma_write(omap_dma_global_context.dma_irqenable_l0,
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IRQENABLE_L0, 0);
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p->dma_write(omap_dma_global_context.dma_irqenable_l1,
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IRQENABLE_L1, 0);
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if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
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p->dma_write(0x3 , IRQSTATUS_L0, 0);
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for (ch = 0; ch < dma_chan_count; ch++)
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if (dma_chan[ch].dev_id != -1)
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omap_clear_dma(ch);
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}
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struct omap_system_dma_plat_info *omap_get_plat_info(void)
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{
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return p;
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@ -2,6 +2,7 @@
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/*
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* OMAP DMAengine support
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*/
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#include <linux/cpu_pm.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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@ -23,12 +24,28 @@
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#define OMAP_SDMA_REQUESTS 127
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#define OMAP_SDMA_CHANNELS 32
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struct omap_dma_config {
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int lch_end;
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unsigned int may_lose_context:1;
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};
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struct omap_dma_context {
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u32 irqenable_l0;
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u32 irqenable_l1;
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u32 ocp_sysconfig;
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u32 gcr;
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};
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struct omap_dmadev {
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struct dma_device ddev;
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spinlock_t lock;
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void __iomem *base;
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const struct omap_dma_reg *reg_map;
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struct omap_system_dma_plat_info *plat;
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const struct omap_dma_config *cfg;
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struct notifier_block nb;
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struct omap_dma_context context;
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int lch_count;
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bool legacy;
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bool ll123_supported;
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struct dma_pool *desc_pool;
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@ -376,6 +393,19 @@ static unsigned omap_dma_get_csr(struct omap_chan *c)
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return val;
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}
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static void omap_dma_clear_lch(struct omap_dmadev *od, int lch)
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{
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struct omap_chan *c;
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int i;
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c = od->lch_map[lch];
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if (!c)
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return;
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for (i = CSDP; i <= od->cfg->lch_end; i++)
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omap_dma_chan_write(c, i, 0);
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}
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static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
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unsigned lch)
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{
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@ -652,6 +682,7 @@ static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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if (ret >= 0) {
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omap_dma_assign(od, c, c->dma_ch);
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pr_info("XXX %s: assigned lch: %i\n", __func__, c->dma_ch);
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if (!od->legacy) {
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unsigned val;
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@ -1453,16 +1484,74 @@ static void omap_dma_free(struct omap_dmadev *od)
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}
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}
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/*
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* We are using IRQENABLE_L1, and legacy DMA code was using IRQENABLE_L0.
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* As the DSP may be using IRQENABLE_L2 and L3, let's not touch those for
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* now. Context save seems to be only currently needed on omap3.
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*/
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static void omap_dma_context_save(struct omap_dmadev *od)
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{
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od->context.irqenable_l0 = omap_dma_glbl_read(od, IRQENABLE_L0);
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od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1);
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od->context.ocp_sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
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od->context.gcr = omap_dma_glbl_read(od, GCR);
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}
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static void omap_dma_context_restore(struct omap_dmadev *od)
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{
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int i;
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omap_dma_glbl_write(od, GCR, od->context.gcr);
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omap_dma_glbl_write(od, OCP_SYSCONFIG, od->context.ocp_sysconfig);
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omap_dma_glbl_write(od, IRQENABLE_L0, od->context.irqenable_l0);
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omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1);
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/* Clear IRQSTATUS_L0 as legacy DMA code is no longer doing it */
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if (od->plat->errata & DMA_ROMCODE_BUG)
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omap_dma_glbl_write(od, IRQSTATUS_L0, 0);
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/* Clear dma channels */
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for (i = 0; i < od->lch_count; i++)
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omap_dma_clear_lch(od, i);
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}
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/* Currently only used for omap3 */
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static int omap_dma_context_notifier(struct notifier_block *nb,
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unsigned long cmd, void *v)
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{
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struct omap_dmadev *od;
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od = container_of(nb, struct omap_dmadev, nb);
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switch (cmd) {
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case CPU_CLUSTER_PM_ENTER:
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omap_dma_context_save(od);
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break;
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case CPU_CLUSTER_PM_ENTER_FAILED:
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case CPU_CLUSTER_PM_EXIT:
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omap_dma_context_restore(od);
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break;
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}
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return NOTIFY_OK;
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}
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#define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
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/*
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* No flags currently set for default configuration as omap1 is still
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* using platform data.
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*/
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static const struct omap_dma_config default_cfg;
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static int omap_dma_probe(struct platform_device *pdev)
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{
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const struct omap_dma_config *conf;
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struct omap_dmadev *od;
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struct resource *res;
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int rc, i, irq;
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u32 lch_count;
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od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
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if (!od)
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@ -1473,6 +1562,12 @@ static int omap_dma_probe(struct platform_device *pdev)
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if (IS_ERR(od->base))
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return PTR_ERR(od->base);
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conf = of_device_get_match_data(&pdev->dev);
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if (conf)
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od->cfg = conf;
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else
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od->cfg = &default_cfg;
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od->plat = omap_get_plat_info();
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if (!od->plat)
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return -EPROBE_DEFER;
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@ -1522,18 +1617,19 @@ static int omap_dma_probe(struct platform_device *pdev)
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/* Number of available logical channels */
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if (!pdev->dev.of_node) {
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lch_count = od->plat->dma_attr->lch_count;
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if (unlikely(!lch_count))
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lch_count = OMAP_SDMA_CHANNELS;
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od->lch_count = od->plat->dma_attr->lch_count;
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if (unlikely(!od->lch_count))
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od->lch_count = OMAP_SDMA_CHANNELS;
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} else if (of_property_read_u32(pdev->dev.of_node, "dma-channels",
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&lch_count)) {
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&od->lch_count)) {
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dev_info(&pdev->dev,
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"Missing dma-channels property, using %u.\n",
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OMAP_SDMA_CHANNELS);
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lch_count = OMAP_SDMA_CHANNELS;
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od->lch_count = OMAP_SDMA_CHANNELS;
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}
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od->lch_map = devm_kcalloc(&pdev->dev, lch_count, sizeof(*od->lch_map),
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od->lch_map = devm_kcalloc(&pdev->dev, od->lch_count,
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sizeof(*od->lch_map),
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GFP_KERNEL);
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if (!od->lch_map)
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return -ENOMEM;
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@ -1605,6 +1701,11 @@ static int omap_dma_probe(struct platform_device *pdev)
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}
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}
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if (od->cfg->may_lose_context) {
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od->nb.notifier_call = omap_dma_context_notifier;
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cpu_pm_register_notifier(&od->nb);
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}
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dev_info(&pdev->dev, "OMAP DMA engine driver%s\n",
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od->ll123_supported ? " (LinkedList1/2/3 supported)" : "");
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@ -1616,6 +1717,9 @@ static int omap_dma_remove(struct platform_device *pdev)
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struct omap_dmadev *od = platform_get_drvdata(pdev);
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int irq;
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if (od->cfg->may_lose_context)
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cpu_pm_unregister_notifier(&od->nb);
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if (pdev->dev.of_node)
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of_dma_controller_free(pdev->dev.of_node);
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@ -1637,12 +1741,34 @@ static int omap_dma_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct omap_dma_config omap2420_data = {
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.lch_end = CCFN,
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};
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static const struct omap_dma_config omap2430_data = {
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.lch_end = CCFN,
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};
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static const struct omap_dma_config omap3430_data = {
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.lch_end = CCFN,
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.may_lose_context = true,
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};
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static const struct omap_dma_config omap3630_data = {
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.lch_end = CCDN,
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.may_lose_context = true,
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};
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static const struct omap_dma_config omap4_data = {
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.lch_end = CCDN,
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};
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static const struct of_device_id omap_dma_match[] = {
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{ .compatible = "ti,omap2420-sdma", },
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{ .compatible = "ti,omap2430-sdma", },
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{ .compatible = "ti,omap3430-sdma", },
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{ .compatible = "ti,omap3630-sdma", },
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{ .compatible = "ti,omap4430-sdma", },
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{ .compatible = "ti,omap2420-sdma", .data = &omap2420_data, },
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{ .compatible = "ti,omap2430-sdma", .data = &omap2430_data, },
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{ .compatible = "ti,omap3430-sdma", .data = &omap3430_data, },
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{ .compatible = "ti,omap3630-sdma", .data = &omap3630_data, },
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{ .compatible = "ti,omap4430-sdma", .data = &omap4_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, omap_dma_match);
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@ -327,8 +327,6 @@ extern dma_addr_t omap_get_dma_src_pos(int lch);
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extern dma_addr_t omap_get_dma_dst_pos(int lch);
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extern int omap_get_dma_active_status(int lch);
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extern int omap_dma_running(void);
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void omap_dma_global_context_save(void);
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void omap_dma_global_context_restore(void);
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#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
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#include <mach/lcd_dma.h>
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