forked from Minki/linux
ath5k: Skip powertable setting when we are on the same channel
* Only set power table if we are changing channel/mode there is no need to recalculate and reset the power table all the time. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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f08fbf6cf4
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4c57581d93
@ -3090,7 +3090,7 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
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*/
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*/
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static int
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static int
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ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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u8 ee_mode, u8 txpower)
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u8 ee_mode, u8 txpower, bool fast)
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{
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{
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struct ath5k_rate_pcal_info rate_info;
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struct ath5k_rate_pcal_info rate_info;
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u8 type;
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u8 type;
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@ -3126,10 +3126,15 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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return -EINVAL;
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return -EINVAL;
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}
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}
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/* FIXME: Only on channel/mode change */
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/* If fast is set it means we are on the same channel/mode
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ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
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* so there is no need to recalculate the powertable, we 'll
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if (ret)
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* just use the cached one */
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return ret;
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if (!fast) {
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ret = ath5k_setup_channel_powertable(ah, channel,
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ee_mode, type);
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if (ret)
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return ret;
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}
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/* Limit max power if we have a CTL available */
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/* Limit max power if we have a CTL available */
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ath5k_get_max_ctl_power(ah, channel);
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ath5k_get_max_ctl_power(ah, channel);
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@ -3210,7 +3215,7 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
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ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
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ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
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"changing txpower to %d\n", txpower);
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"changing txpower to %d\n", txpower);
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return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
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return ath5k_hw_txpower(ah, channel, ee_mode, txpower, true);
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}
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}
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/*************\
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/*************\
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@ -3220,13 +3225,42 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
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int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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u8 mode, u8 ee_mode, u8 freq)
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u8 mode, u8 ee_mode, u8 freq)
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{
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{
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struct ieee80211_channel *curr_channel;
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int ret, i;
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int ret, i;
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u32 phy_tst1;
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u32 phy_tst1;
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bool fast_txp;
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ret = 0;
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ret = 0;
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/*
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/*
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* 5211/5212 Specific
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* If we don't change channel/mode skip
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* tx powertable calculation and use the
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* cached one.
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*/
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curr_channel = ah->ah_current_channel;
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if ((channel->hw_value == curr_channel->hw_value) &&
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(channel->center_freq == curr_channel->center_freq))
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fast_txp = true;
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else
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fast_txp = false;
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/*
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* Set TX power
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*
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* Note: We need to do that before we set
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* RF buffer settings on 5211/5212+ so that we
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* properly set curve indices.
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*/
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ret = ath5k_hw_txpower(ah, channel, ee_mode,
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ah->ah_txpower.txp_max_pwr / 2,
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fast_txp);
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if (ret)
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return ret;
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/*
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* For 5210 we do all initialization using
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* initvals, so we don't have to modify
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* any settings (5210 also only supports
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* a/aturbo modes)
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*/
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*/
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if (ah->ah_version != AR5K_AR5210) {
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if (ah->ah_version != AR5K_AR5210) {
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@ -3240,14 +3274,6 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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mdelay(1);
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mdelay(1);
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/*
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* Set TX power
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*/
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ret = ath5k_hw_txpower(ah, channel, ee_mode,
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ah->ah_txpower.txp_max_pwr / 2);
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if (ret)
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return ret;
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/*
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/*
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* Write RF buffer
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* Write RF buffer
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*/
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*/
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@ -3255,7 +3281,6 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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if (ret)
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if (ret)
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return ret;
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return ret;
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/* Write OFDM timings on 5212*/
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/* Write OFDM timings on 5212*/
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if (ah->ah_version == AR5K_AR5212 &&
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if (ah->ah_version == AR5K_AR5212 &&
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channel->hw_value & CHANNEL_OFDM) {
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channel->hw_value & CHANNEL_OFDM) {
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@ -3284,12 +3309,6 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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}
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}
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} else {
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} else {
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/*
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* For 5210 we do all initialization using
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* initvals, so we don't have to modify
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* any settings (5210 also only supports
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* a/aturbo modes)
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*/
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mdelay(1);
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mdelay(1);
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/* Disable phy and wait */
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/* Disable phy and wait */
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
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ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
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