From 4bb1a1089e321d685967032497f4363081eab3a9 Mon Sep 17 00:00:00 2001
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 13 May 2009 15:59:56 -0700
Subject: [PATCH] MIPS: Move Cavium CP0 hwrena impl bits to
cpu-feature-overrides.h
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
.../include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 +
arch/mips/kernel/traps.c | 4 ----
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bb291f41b6a3..3d830756b13a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -53,6 +53,7 @@
#define cpu_has_userlocal 0
#define cpu_has_vint 0
#define cpu_has_veic 0
+#define cpu_hwrena_impl_bits 0xc0000000
#define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f54871797ab9..08f1edf355e8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
write_c0_hwrena(enable);
}
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
#ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) {
#endif /* CONFIG_MIPS_MT_SMTC */