PCI: pciehp: Document struct slot and struct controller
Document the driver's data structures to lower the barrier to entry for contributors. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -57,11 +57,26 @@ do { \
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dev_warn(&ctrl->pcie->device, format, ## arg)
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dev_warn(&ctrl->pcie->device, format, ## arg)
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#define SLOT_NAME_SIZE 10
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#define SLOT_NAME_SIZE 10
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/**
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* struct slot - PCIe hotplug slot
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* @state: current state machine position
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* @ctrl: pointer to the slot's controller structure
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* @hotplug_slot: pointer to the structure registered with the PCI hotplug core
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* @work: work item to turn the slot on or off after 5 seconds in response to
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* an Attention Button press
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* @lock: protects reads and writes of @state;
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* protects scheduling, execution and cancellation of @work
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* @hotplug_lock: serializes calls to pciehp_enable_slot() and
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* pciehp_disable_slot()
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* @wq: work queue on which @work is scheduled;
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* also used to queue interrupt events and slot enablement and disablement
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*/
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struct slot {
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struct slot {
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u8 state;
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u8 state;
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struct controller *ctrl;
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struct controller *ctrl;
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struct hotplug_slot *hotplug_slot;
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struct hotplug_slot *hotplug_slot;
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struct delayed_work work; /* work for button event */
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struct delayed_work work;
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struct mutex lock;
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struct mutex lock;
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struct mutex hotplug_lock;
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struct mutex hotplug_lock;
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struct workqueue_struct *wq;
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struct workqueue_struct *wq;
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@ -73,11 +88,36 @@ struct event_info {
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struct work_struct work;
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struct work_struct work;
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};
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};
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/**
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* struct controller - PCIe hotplug controller
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* @ctrl_lock: serializes writes to the Slot Control register
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* @pcie: pointer to the controller's PCIe port service device
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* @slot: pointer to the controller's slot structure
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* @queue: wait queue to wake up on reception of a Command Completed event,
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* used for synchronous writes to the Slot Control register
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* @slot_cap: cached copy of the Slot Capabilities register
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* @slot_ctrl: cached copy of the Slot Control register
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* @poll_timer: timer to poll for slot events if no IRQ is available,
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* enabled with pciehp_poll_mode module parameter
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* @cmd_started: jiffies when the Slot Control register was last written;
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* the next write is allowed 1 second later, absent a Command Completed
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* interrupt (PCIe r4.0, sec 6.7.3.2)
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* @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
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* on reception of a Command Completed event
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* @link_active_reporting: cached copy of Data Link Layer Link Active Reporting
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* Capable bit in Link Capabilities register; if this bit is zero, the
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* Data Link Layer Link Active bit in the Link Status register will never
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* be set and the driver is thus confined to wait 1 second before assuming
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* the link to a hotplugged device is up and accessing it
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* @notification_enabled: whether the IRQ was requested successfully
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* @power_fault_detected: whether a power fault was detected by the hardware
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* that has not yet been cleared by the user
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*/
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struct controller {
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struct controller {
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struct mutex ctrl_lock; /* controller lock */
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struct mutex ctrl_lock;
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struct pcie_device *pcie; /* PCI Express port service */
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struct pcie_device *pcie;
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struct slot *slot;
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struct slot *slot;
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wait_queue_head_t queue; /* sleep & wake process */
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wait_queue_head_t queue;
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u32 slot_cap;
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u32 slot_cap;
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u16 slot_ctrl;
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u16 slot_ctrl;
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struct timer_list poll_timer;
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struct timer_list poll_timer;
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