forked from Minki/linux
mtd: gpmi: do not include the mxs.h
The mxs.h does not exit in the mx6q. So rewrite the __mxs_clrl()/__mxs_setl() and remove the mxs.h. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -21,7 +21,6 @@
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#include <linux/mtd/gpmi-nand.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <mach/mxs.h>
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#include "gpmi-nand.h"
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#include "gpmi-regs.h"
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@ -37,6 +36,8 @@ struct timing_threshod timing_default_threshold = {
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.max_dll_delay_in_ns = 16,
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};
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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@ -47,7 +48,7 @@ static int clear_poll_bit(void __iomem *addr, u32 mask)
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int timeout = 0x400;
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/* clear the bit */
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__mxs_clrl(mask, addr);
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writel(mask, addr + MXS_CLR_ADDR);
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/*
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* SFTRST needs 3 GPMI clocks to settle, the reference manual
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@ -92,11 +93,11 @@ static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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goto error;
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/* clear CLKGATE */
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__mxs_clrl(MODULE_CLKGATE, reset_addr);
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writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
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if (!just_enable) {
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/* set SFTRST to reset the block */
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__mxs_setl(MODULE_SFTRST, reset_addr);
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writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
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udelay(1);
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/* poll CLKGATE becoming set */
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