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ARM: SoC non-critical bug fixes for 3.18

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These are bug fixes for harmless problems that were not important
 enough to get fixed in 3.17. The majority of these are OMAP specific,
 but there are also a couple for Marvell mvebu, cns3xxx, and others,
 as well as some updates for the MAINTAINERS file.
 
 In particular, Robert Jarzmik and Daniel Mack now volunteered to help
 out maintaining the PXA platform, Krzysztof Halasa took over the
 cns3xxx platform, Carlo Caione is the maintainer for the new Amlogic
 meson platform, and Matthias Brugger is now listed for the mediatek
 platform he recently contributed.
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Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical bug fixes from Arnd Bergmann:
 "These are bug fixes for harmless problems that were not important
  enough to get fixed in 3.17.  The majority of these are OMAP specific,
  but there are also a couple for Marvell mvebu, cns3xxx, and others, as
  well as some updates for the MAINTAINERS file.

  In particular, Robert Jarzmik and Daniel Mack now volunteered to help
  out maintaining the PXA platform, Krzysztof Halasa took over the
  cns3xxx platform, Carlo Caione is the maintainer for the new Amlogic
  meson platform, and Matthias Brugger is now listed for the mediatek
  platform he recently contributed"

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
  MAINTAINERS: update Shawn's email address
  MAINTAINERS: condense some Tegra related entries
  MAINTAINERS: add Alexandre Courbot for Tegra
  MAINTAINERS: CNS3xxx and IXP4xx update.
  MAINTAINERS: Add maintainers entry for Mediatek SoCs
  arm, vt8500, LLVMLlinux: Use mcr instead of mcr% for mach-vt8500
  MAINTAINERS: add a third maintainer to mach-bcm
  CNS3xxx: Fix PCIe read size limit.
  CNS3xxx: Fix logical PCIe topology.
  CNS3xxx: Fix debug UART.
  MAINTAINERS: Add entry for the Amlogic MesonX SoCs
  MAINTAINERS: update ARM pxa maintainers
  ARM: at91/PMC: don't forget to write PMC_PCDR register to disable clocks
  ARM: at91: fix at91sam9263ek DT mmc pinmuxing settings
  ARM: mvebu: Netgear RN102: Use Hardware BCH ECC
  ARM: Kirkwood: Fix DT based DSA.
  ARM: OMAP2+: make of_device_ids const
  ARM: omap2: make arrays containing machine compatible strings const
  ARM: LPC32xx: Fix reset function
  ARM: mvebu: Netgear RN2120: Use Hardware BCH ECC
  ...
This commit is contained in:
Linus Torvalds 2014-10-08 17:03:09 -04:00
commit 4a4743e840
48 changed files with 329 additions and 204 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
MAINTAINERS
View File

@ -846,6 +846,12 @@ M: Emilio López <emilio@elopez.com.ar>
S: Maintained
F: drivers/clk/sunxi/
ARM/Amlogic MesonX SoC support
M: Carlo Caione <carlo@caione.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: meson[x68]
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
@ -872,10 +878,9 @@ S: Maintained
F: arch/arm/mach-highbank/
ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
M: Anton Vorontsov <anton@enomsg.org>
M: Krzysztof Halasa <khalasa@piap.pl>
S: Maintained
F: arch/arm/mach-cns3xxx/
T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE
M: Alexander Shiyan <shc_work@mail.ru>
@ -975,7 +980,7 @@ F: arch/arm/include/asm/hardware/dec21285.h
F: arch/arm/mach-footbridge/
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
M: Shawn Guo <shawn.guo@freescale.com>
M: Shawn Guo <shawn.guo@linaro.org>
M: Sascha Hauer <kernel@pengutronix.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
@ -1060,7 +1065,7 @@ S: Maintained
ARM/INTEL IXP4XX ARM ARCHITECTURE
M: Imre Kaloz <kaloz@openwrt.org>
M: Krzysztof Halasa <khc@pm.waw.pl>
M: Krzysztof Halasa <khalasa@piap.pl>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-ixp4xx/
@ -1156,6 +1161,16 @@ W: http://www.digriz.org.uk/ts78xx/kernel
S: Maintained
F: arch/arm/mach-orion5x/ts78xx-*
ARM/Mediatek SoC support
M: Matthias Brugger <matthias.bgg@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/mt6*
F: arch/arm/boot/dts/mt8*
F: arch/arm/mach-mediatek/
N: mtk
K: mediatek
ARM/MICREL KS8695 ARCHITECTURE
M: Greg Ungerer <gerg@uclinux.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1367,7 +1382,6 @@ F: arch/arm/boot/dts/sh*
F: arch/arm/configs/ape6evm_defconfig
F: arch/arm/configs/armadillo800eva_defconfig
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/genmai_defconfig
F: arch/arm/configs/koelsch_defconfig
F: arch/arm/configs/kzm9g_defconfig
F: arch/arm/configs/lager_defconfig
@ -2021,6 +2035,7 @@ F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
M: Christian Daudt <bcm@fixthebug.org>
M: Matt Porter <mporter@linaro.org>
M: Florian Fainelli <f.fainelli@gmail.com>
L: bcm-kernel-feedback-list@broadcom.com
T: git git://github.com/broadcom/mach-bcm
S: Maintained
@ -4796,7 +4811,7 @@ S: Odd fixes
F: drivers/dma/iop-adma.c
INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
M: Krzysztof Halasa <khc@pm.waw.pl>
M: Krzysztof Halasa <khalasa@piap.pl>
S: Maintained
F: arch/arm/mach-ixp4xx/include/mach/qmgr.h
F: arch/arm/mach-ixp4xx/include/mach/npe.h
@ -7322,12 +7337,12 @@ F: drivers/video/backlight/pwm_bl.c
F: include/linux/pwm_backlight.h
PXA2xx/PXA3xx SUPPORT
M: Eric Miao <eric.y.miao@gmail.com>
M: Russell King <linux@arm.linux.org.uk>
M: Daniel Mack <daniel@zonque.org>
M: Haojian Zhuang <haojian.zhuang@gmail.com>
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/hzhuang1/linux.git
T: git git://git.linaro.org/people/ycmiao/pxa-linux.git
T: git git://github.com/rjarzmik/linux.git
S: Maintained
F: arch/arm/mach-pxa/
F: drivers/pcmcia/pxa2xx*
@ -9044,17 +9059,13 @@ F: drivers/media/rc/ttusbir.c
TEGRA ARCHITECTURE SUPPORT
M: Stephen Warren <swarren@wwwdotorg.org>
M: Thierry Reding <thierry.reding@gmail.com>
M: Alexandre Courbot <gnurou@gmail.com>
L: linux-tegra@vger.kernel.org
Q: http://patchwork.ozlabs.org/project/linux-tegra/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
S: Supported
N: [^a-z]tegra
TEGRA ASOC DRIVER
M: Stephen Warren <swarren@wwwdotorg.org>
S: Supported
F: sound/soc/tegra/
TEGRA CLOCK DRIVER
M: Peter De Schrijver <pdeschrijver@nvidia.com>
M: Prashant Gaikwad <pgaikwad@nvidia.com>
@ -9066,11 +9077,6 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
S: Supported
F: drivers/dma/tegra20-apb-dma.c
TEGRA GPIO DRIVER
M: Stephen Warren <swarren@wwwdotorg.org>
S: Supported
F: drivers/gpio/gpio-tegra.c
TEGRA I2C DRIVER
M: Laxman Dewangan <ldewangan@nvidia.com>
S: Supported
@ -9087,11 +9093,6 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
S: Supported
F: drivers/input/keyboard/tegra-kbc.c
TEGRA PINCTRL DRIVER
M: Stephen Warren <swarren@wwwdotorg.org>
S: Supported
F: drivers/pinctrl/pinctrl-tegra*
TEGRA PWM DRIVER
M: Thierry Reding <thierry.reding@gmail.com>
S: Supported

7
arch/arm/Kconfig.debug
View File

@ -147,7 +147,7 @@ choice
config DEBUG_CNS3XXX
bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
depends on ARCH_CNS3XXX
select DEBUG_UART_PL01X
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to the CNS3xxx UART0.
@ -1068,7 +1068,7 @@ config DEBUG_UART_PHYS
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
default 0x10124000 if DEBUG_RK3X_UART0
@ -1094,6 +1094,7 @@ config DEBUG_UART_PHYS
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0x7c0003f8 if FOOTBRIDGE
default 0x78000000 if DEBUG_CNS3XXX
default 0x80070000 if DEBUG_IMX23_UART
default 0x80074000 if DEBUG_IMX28_UART
default 0x80230000 if DEBUG_PICOXCELL_UART
@ -1133,7 +1134,6 @@ config DEBUG_UART_VIRT
default 0xe0010fe0 if ARCH_RPC
default 0xe1000000 if DEBUG_MSM_UART
default 0xf0000be0 if ARCH_EBSA110
default 0xf0009000 if DEBUG_CNS3XXX
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835
default 0xf1000300 if DEBUG_BCM_5301X
@ -1155,6 +1155,7 @@ config DEBUG_UART_VIRT
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xfa71e000 if DEBUG_QCOM_UARTDM
default 0xfb002000 if DEBUG_CNS3XXX
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX

4
arch/arm/boot/dts/Makefile
View File

@ -144,8 +144,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \
kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-a0.dtb \
kirkwood-rd88f6281-a1.dtb \
kirkwood-rd88f6281-z0.dtb \
kirkwood-rd88f6281-a.dtb \
kirkwood-rs212.dtb \
kirkwood-rs409.dtb \
kirkwood-rs411.dtb \

3
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -7,9 +7,6 @@
*/
/ {
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;

5
arch/arm/boot/dts/am335x-bone.dts
View File

@ -10,6 +10,11 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
/ {
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
};
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;

5
arch/arm/boot/dts/am335x-boneblack.dts
View File

@ -10,6 +10,11 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
/ {
model = "TI AM335x BeagleBone Black";
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

4
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View File

@ -143,6 +143,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
/* Use Hardware BCH ECC */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */

4
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View File

@ -145,6 +145,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
/* Use Hardware BCH ECC */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */

4
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View File

@ -223,6 +223,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
/* Use Hardware BCH ECC */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */

2
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -834,6 +834,7 @@
compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci0_clk>;
@ -845,6 +846,7 @@
compatible = "atmel,hsmci";
reg = <0xfff84000 0x600>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci1_clk>;

16
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
View File

@ -123,11 +123,11 @@
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&ethphy0>;
dsa,ethernet = <&eth0port>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
@ -169,17 +169,13 @@
&mdio {
status = "okay";
ethphy0: ethernet-phy@ff {
reg = <0xff>; /* No phy attached */
speed = <1000>;
duplex = <1>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
speed = <1000>;
duplex = <1>;
};
};

43
arch/arm/boot/dts/kirkwood-rd88f6281-a.dts Normal file
View File

@ -0,0 +1,43 @@
/*
* Marvell RD88F6181 A Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A0 or
* higher stepping of the SoC. The ethernet switch does not have a
* "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
reg = <10 0>; /* MDIO address 10, switch 0 in tree */
};
};
};
&mdio {
status = "okay";
ethphy1: ethernet-phy@11 {
reg = <11>;
};
};
&eth1 {
status = "okay";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
};
};

26
arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
View File

@ -1,26 +0,0 @@
/*
* Marvell RD88F6181 A0 Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A0 variant of
* the SoC. The ethernet switch does not have a "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A0 SoC";
compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
reg = <10 0>; /* MDIO address 10, switch 0 in tree */
};
};
};

18
arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts → arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
View File

@ -1,5 +1,5 @@
/*
* Marvell RD88F6181 A1 Board descrition
* Marvell RD88F6181 Z0 stepping descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
@ -7,17 +7,17 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions for the board with the A1 variant of
* the SoC. The ethernet switch has a "wan" port.
*/
* This file contains the definitions for the board using the Z0
* stepping of the SoC. The ethernet switch has a "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with A1 SoC";
compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
model = "Marvell RD88f6281 Reference design, with Z0 SoC";
compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
dsa@0 {
switch@0 {
@ -28,4 +28,8 @@
};
};
};
};
};
&eth1 {
status = "disabled";
};

27
arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
View File

@ -37,7 +37,6 @@
ocp@f1000000 {
pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_sdio_cd>;
pinctrl-names = "default";
pmx_sdio_cd: pmx-sdio-cd {
@ -69,8 +68,8 @@
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth0>;
dsa,mii-bus = <&ethphy1>;
dsa,ethernet = <&eth0port>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
@ -119,35 +118,19 @@
};
partition@300000 {
label = "data";
label = "rootfs";
reg = <0x0300000 0x500000>;
};
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@ff {
reg = <0xff>; /* No PHY attached */
speed = <1000>;
duple = <1>;
};
};
&eth0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
};
};
&eth1 {
status = "okay";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
speed = <1000>;
duplex = <1>;
};
};

4
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -309,7 +309,7 @@
marvell,tx-checksum-limit = <1600>;
status = "disabled";
ethernet0-port@0 {
eth0port: ethernet0-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <11>;
@ -342,7 +342,7 @@
pinctrl-names = "default";
status = "disabled";
ethernet1-port@0 {
eth1port: ethernet1-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <15>;

3
arch/arm/boot/dts/omap4-panda-common.dtsi
View File

@ -8,9 +8,6 @@
#include "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */

5
arch/arm/boot/dts/omap4-panda-es.dts
View File

@ -10,6 +10,11 @@
#include "omap4460.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard-ES";
compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
};
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {
ti,model = "PandaBoardES";

5
arch/arm/boot/dts/omap4-panda.dts
View File

@ -9,3 +9,8 @@
#include "omap443x.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
};

1
arch/arm/mach-at91/clock.c
View File

@ -962,6 +962,7 @@ static int __init at91_clock_reset(void)
}
at91_pmc_write(AT91_PMC_SCDR, scdr);
at91_pmc_write(AT91_PMC_PCDR, pcdr);
if (cpu_is_sama5d3())
at91_pmc_write(AT91_PMC_PCDR1, pcdr1);

1
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@ -250,5 +250,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = cns3420_init,
.init_late = cns3xxx_pcie_init_late,
.restart = cns3xxx_restart,
MACHINE_END

1
arch/arm/mach-cns3xxx/core.c
View File

@ -404,5 +404,6 @@ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = cns3xxx_init,
.init_late = cns3xxx_pcie_init_late,
.restart = cns3xxx_restart,
MACHINE_END

6
arch/arm/mach-cns3xxx/core.h
View File

@ -21,6 +21,12 @@ void __init cns3xxx_l2x0_init(void);
static inline void cns3xxx_l2x0_init(void) {}
#endif /* CONFIG_CACHE_L2X0 */
#ifdef CONFIG_PCI
extern void __init cns3xxx_pcie_init_late(void);
#else
static inline void __init cns3xxx_pcie_init_late(void) {}
#endif
void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);

53
arch/arm/mach-cns3xxx/pcie.c
View File

@ -60,11 +60,10 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
int busno = bus->number;
int slot = PCI_SLOT(devfn);
int offset;
void __iomem *base;
/* If there is no link, just show the CNS PCI bridge. */
if (!cnspci->linked && (busno > 0 || slot > 0))
if (!cnspci->linked && busno > 0)
return NULL;
/*
@ -72,22 +71,21 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
* we still want to access it. For this to work, we must place
* the first device on the same bus as the CNS PCI bridge.
*/
if (busno == 0) { /* directly connected PCIe bus */
switch (slot) {
case 0: /* host bridge device, function 0 only */
if (busno == 0) { /* internal PCIe bus, host bridge device */
if (devfn == 0) /* device# and function# are ignored by hw */
base = cnspci->host_regs;
break;
case 1: /* directly connected device */
base = cnspci->cfg0_regs;
break;
default:
else
return NULL; /* no such device */
}
} else /* remote PCI bus */
base = cnspci->cfg1_regs;
offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
return base + offset;
} else if (busno == 1) { /* directly connected PCIe device */
if (slot == 0) /* device# is ignored by hw */
base = cnspci->cfg0_regs;
else
return NULL; /* no such device */
} else /* remote PCI bus */
base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
return base + (where & 0xffc) + (devfn << 12);
}
static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@ -167,7 +165,7 @@ static struct pci_ops cns3xxx_pcie_ops = {
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
int irq = cnspci->irqs[slot];
int irq = cnspci->irqs[!!dev->bus->number];
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
@ -297,15 +295,19 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
return;
/* Set Device Max_Read_Request_Size to 128 byte */
devfn = PCI_DEVFN(1, 0);
bus.number = 1; /* directly connected PCIe device */
devfn = PCI_DEVFN(0, 0);
pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
if (!(dc & (0x3 << 12)))
pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
if (dc & PCI_EXP_DEVCTL_READRQ) {
dc &= ~PCI_EXP_DEVCTL_READRQ;
pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
if (dc & PCI_EXP_DEVCTL_READRQ)
pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
else
pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
}
/* Disable PCIe0 Interrupt Mask INTA to INTD */
__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
}
@ -318,7 +320,7 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
return 0;
}
static int __init cns3xxx_pcie_init(void)
void __init cns3xxx_pcie_init_late(void)
{
int i;
@ -337,7 +339,4 @@ static int __init cns3xxx_pcie_init(void)
}
pci_assign_unassigned_resources();
return 0;
}
device_initcall(cns3xxx_pcie_init);

15
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -35,6 +35,7 @@
#include <linux/platform_data/uio_pruss.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/tps6507x.h>
#include <linux/regulator/fixed.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/wl12xx.h>
@ -842,6 +843,16 @@ static int da850_lcd_hw_init(void)
return 0;
}
/* Fixed regulator support */
static struct regulator_consumer_supply fixed_supplies[] = {
/* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
REGULATOR_SUPPLY("AVDD", "1-0018"),
REGULATOR_SUPPLY("DRVDD", "1-0018"),
/* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
REGULATOR_SUPPLY("DVDD", "1-0018"),
};
/* TPS65070 voltage regulator support */
/* 3.3V */
@ -865,6 +876,7 @@ static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
{
.supply = "dvdd3318_c",
},
REGULATOR_SUPPLY("IOVDD", "1-0018"),
};
/* 1.2V */
@ -936,6 +948,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
.consumer_supplies = tps65070_dcdc2_consumers,
@ -1446,6 +1459,8 @@ static __init void da850_evm_init(void)
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
ret = pmic_tps65070_init();
if (ret)
pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);

29
arch/arm/mach-lpc32xx/common.c
View File

@ -56,20 +56,6 @@ int clk_is_sysclk_mainosc(void)
return 0;
}
/*
* System reset via the watchdog timer
*/
static void lpc32xx_watchdog_reset(void)
{
/* Make sure WDT clocks are enabled */
__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
LPC32XX_CLKPWR_TIMER_CLK_CTRL);
/* Instant assert of RESETOUT_N with pulse length 1mS */
__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
}
/*
* Detects and returns IRAM size for the device variation
*/
@ -210,16 +196,13 @@ void __init lpc32xx_map_io(void)
void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
{
switch (mode) {
case REBOOT_SOFT:
case REBOOT_HARD:
lpc32xx_watchdog_reset();
break;
/* Make sure WDT clocks are enabled */
__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
LPC32XX_CLKPWR_TIMER_CLK_CTRL);
default:
/* Do nothing */
break;
}
/* Instant assert of RESETOUT_N with pulse length 1mS */
__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
/* Wait for watchdog to reset system */
while (1)

26
arch/arm/mach-omap2/board-generic.c
View File

@ -27,7 +27,7 @@
#define gic_of_init NULL
#endif
static struct of_device_id omap_dt_match_table[] __initdata = {
static const struct of_device_id omap_dt_match_table[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },
{ }
@ -43,7 +43,7 @@ static void __init omap_generic_init(void)
}
#ifdef CONFIG_SOC_OMAP2420
static const char *omap242x_boards_compat[] __initconst = {
static const char *const omap242x_boards_compat[] __initconst = {
"ti,omap2420",
NULL,
};
@ -62,7 +62,7 @@ MACHINE_END
#endif
#ifdef CONFIG_SOC_OMAP2430
static const char *omap243x_boards_compat[] __initconst = {
static const char *const omap243x_boards_compat[] __initconst = {
"ti,omap2430",
NULL,
};
@ -81,7 +81,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_OMAP3
static const char *omap3_boards_compat[] __initconst = {
static const char *const omap3_boards_compat[] __initconst = {
"ti,omap3430",
"ti,omap3",
NULL,
@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.restart = omap3xxx_restart,
MACHINE_END
static const char *omap36xx_boards_compat[] __initconst = {
static const char *const omap36xx_boards_compat[] __initconst = {
"ti,omap36xx",
NULL,
};
@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
.restart = omap3xxx_restart,
MACHINE_END
static const char *omap3_gp_boards_compat[] __initconst = {
static const char *const omap3_gp_boards_compat[] __initconst = {
"ti,omap3-beagle",
"timll,omap3-devkit8000",
NULL,
@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
.restart = omap3xxx_restart,
MACHINE_END
static const char *am3517_boards_compat[] __initconst = {
static const char *const am3517_boards_compat[] __initconst = {
"ti,am3517",
NULL,
};
@ -157,7 +157,7 @@ MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
static const char *am33xx_boards_compat[] __initconst = {
static const char *const am33xx_boards_compat[] __initconst = {
"ti,am33xx",
NULL,
};
@ -177,7 +177,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_OMAP4
static const char *omap4_boards_compat[] __initconst = {
static const char *const omap4_boards_compat[] __initconst = {
"ti,omap4460",
"ti,omap4430",
"ti,omap4",
@ -199,7 +199,7 @@ MACHINE_END
#endif
#ifdef CONFIG_SOC_OMAP5
static const char *omap5_boards_compat[] __initconst = {
static const char *const omap5_boards_compat[] __initconst = {
"ti,omap5432",
"ti,omap5430",
"ti,omap5",
@ -221,7 +221,7 @@ MACHINE_END
#endif
#ifdef CONFIG_SOC_AM43XX
static const char *am43_boards_compat[] __initconst = {
static const char *const am43_boards_compat[] __initconst = {
"ti,am4372",
"ti,am43",
NULL,
@ -240,7 +240,7 @@ MACHINE_END
#endif
#ifdef CONFIG_SOC_DRA7XX
static const char *dra74x_boards_compat[] __initconst = {
static const char *const dra74x_boards_compat[] __initconst = {
"ti,dra742",
"ti,dra7",
NULL,
@ -259,7 +259,7 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
.restart = omap44xx_restart,
MACHINE_END
static const char *dra72x_boards_compat[] __initconst = {
static const char *const dra72x_boards_compat[] __initconst = {
"ti,dra722",
NULL,
};

2
arch/arm/mach-omap2/common.h
View File

@ -307,7 +307,7 @@ static inline void omap4_cpu_resume(void)
#endif
void pdata_quirks_init(struct of_device_id *);
void pdata_quirks_init(const struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));

2
arch/arm/mach-omap2/gpmc.c
View File

@ -1243,7 +1243,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
}
#ifdef CONFIG_OF
static struct of_device_id gpmc_dt_ids[] = {
static const struct of_device_id gpmc_dt_ids[] = {
{ .compatible = "ti,omap2420-gpmc" },
{ .compatible = "ti,omap2430-gpmc" },
{ .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */

2
arch/arm/mach-omap2/irq.c
View File

@ -289,7 +289,7 @@ int __init intc_of_init(struct device_node *node,
return 0;
}
static struct of_device_id irq_match[] __initdata = {
static const struct of_device_id irq_match[] __initconst = {
{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
{ }
};

4
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -298,6 +298,10 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
/* Use the achievable power state for the domain */
power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
false, power_state);
if (power_state == PWRDM_POWER_OFF)
cpu_state = 1;

2
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -405,7 +405,7 @@ static void pdata_quirks_check(struct pdata_init *quirks)
}
}
void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
{
omap_sdrc_init(NULL, NULL);
pdata_quirks_check(auxdata_quirks);

9
arch/arm/mach-omap2/pm44xx.c
View File

@ -29,6 +29,7 @@ u16 pm44xx_errata;
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
u32 next_logic_state;
#ifdef CONFIG_SUSPEND
u32 saved_state;
u32 saved_logic_state;
@ -54,7 +55,7 @@ static int omap4_pm_suspend(void)
/* Set targeted power domain states by suspend */
list_for_each_entry(pwrst, &pwrst_list, node) {
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
}
/*
@ -120,7 +121,11 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
return -ENOMEM;
pwrst->pwrdm = pwrdm;
pwrst->next_state = PWRDM_POWER_RET;
pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
PWRDM_POWER_RET);
pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
PWRDM_POWER_OFF);
list_add(&pwrst->node, &pwrst_list);
return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);

79
arch/arm/mach-omap2/powerdomain.c
View File

@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
return -EINVAL;
for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
if (pwrdm->pwrdm_clkdms[i])
ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
return ret;
}
@ -1079,6 +1080,82 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
return 0;
}
/**
* pwrdm_get_valid_lp_state() - Find best match deep power state
* @pwrdm: power domain for which we want to find best match
* @is_logic_state: Are we looking for logic state match here? Should
* be one of PWRDM_xxx macro values
* @req_state: requested power state
*
* Returns: closest match for requested power state. default fallback
* is RET for logic state and ON for power state.
*
* This does a search from the power domain data looking for the
* closest valid power domain state that the hardware can achieve.
* PRCM definitions for PWRSTCTRL allows us to program whatever
* configuration we'd like, and PRCM will actually attempt such
* a transition, however if the powerdomain does not actually support it,
* we endup with a hung system. The valid power domain states are already
* available in our powerdomain data files. So this function tries to do
* the following:
* a) find if we have an exact match to the request - no issues.
* b) else find if a deeper power state is possible.
* c) failing which, it tries to find closest higher power state for the
* request.
*/
u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
bool is_logic_state, u8 req_state)
{
u8 pwrdm_states = is_logic_state ? pwrdm->pwrsts_logic_ret :
pwrdm->pwrsts;
/* For logic, ret is highest and others, ON is highest */
u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON;
u8 new_pwrst;
bool found;
/* If it is already supported, nothing to search */
if (pwrdm_states & BIT(req_state))
return req_state;
if (!req_state)
goto up_search;
/*
* So, we dont have a exact match
* Can we get a deeper power state match?
*/
new_pwrst = req_state - 1;
found = true;
while (!(pwrdm_states & BIT(new_pwrst))) {
/* No match even at OFF? Not available */
if (new_pwrst == PWRDM_POWER_OFF) {
found = false;
break;
}
new_pwrst--;
}
if (found)
goto done;
up_search:
/* OK, no deeper ones, can we get a higher match? */
new_pwrst = req_state + 1;
while (!(pwrdm_states & BIT(new_pwrst))) {
if (new_pwrst > PWRDM_POWER_ON) {
WARN(1, "powerdomain: %s: Fix max powerstate to ON\n",
pwrdm->name);
return PWRDM_POWER_ON;
}
if (new_pwrst == default_pwrst)
break;
new_pwrst++;
}
done:
return new_pwrst;
}
/**
* omap_set_pwrdm_state - change a powerdomain's current power state
* @pwrdm: struct powerdomain * to change the power state of

4
arch/arm/mach-omap2/powerdomain.h
View File

@ -39,6 +39,7 @@
#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
/*
@ -219,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
bool is_logic_state, u8 req_state);
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_pwrst(struct powerdomain *pwrdm);

12
arch/arm/mach-omap2/powerdomains54xx_data.c
View File

@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = {
.prcm_offs = OMAP54XX_PRM_CORE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = {
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = {
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = {
.prcm_offs = OMAP54XX_PRM_MPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */

14
arch/arm/mach-omap2/powerdomains7xx_data.c
View File

@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = DRA7XX_PRM_CORE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts = PWRSTS_INA_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = {
.name = "cpu0_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = {
.name = "cpu1_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = {
.prcm_offs = DRA7XX_PRM_MPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */

2
arch/arm/mach-omap2/prm_common.c
View File

@ -467,7 +467,7 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
static struct of_device_id omap_prcm_dt_match_table[] = {
static const struct of_device_id omap_prcm_dt_match_table[] = {
{ .compatible = "ti,am3-prcm" },
{ .compatible = "ti,am3-scrm" },
{ .compatible = "ti,am4-prcm" },

6
arch/arm/mach-omap2/timer.c
View File

@ -141,7 +141,7 @@ static struct property device_disabled = {
.value = "disabled",
};
static struct of_device_id omap_timer_match[] __initdata = {
static const struct of_device_id omap_timer_match[] __initconst = {
{ .compatible = "ti,omap2420-timer", },
{ .compatible = "ti,omap3430-timer", },
{ .compatible = "ti,omap4430-timer", },
@ -162,7 +162,7 @@ static struct of_device_id omap_timer_match[] __initdata = {
* the timer node in device-tree as disabled, to prevent the kernel from
* registering this timer as a platform device and so no one else can use it.
*/
static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
const char *property)
{
struct device_node *np;
@ -388,7 +388,7 @@ static u64 notrace dmtimer_read_sched_clock(void)
return 0;
}
static struct of_device_id omap_counter_match[] __initdata = {
static const struct of_device_id omap_counter_match[] __initconst = {
{ .compatible = "ti,omap-counter32k", },
{ }
};

9
arch/arm/mach-spear/Kconfig
View File

@ -4,7 +4,6 @@
menuconfig PLAT_SPEAR
bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
default PLAT_SPEAR_SINGLE
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKSRC_MMIO
@ -13,7 +12,7 @@ if PLAT_SPEAR
config ARCH_SPEAR13XX
bool "ST SPEAr13xx"
depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
depends on ARCH_MULTI_V7
select ARM_GIC
select GPIO_SPEAR_SPICS
select HAVE_ARM_SCU if SMP
@ -44,7 +43,7 @@ endif #ARCH_SPEAR13XX
config ARCH_SPEAR3XX
bool "ST SPEAr3xx"
depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
depends on ARCH_MULTI_V5
depends on !ARCH_SPEAR13XX
select ARM_VIC
select PINCTRL
@ -75,7 +74,7 @@ endif
config ARCH_SPEAR6XX
bool "ST SPEAr6XX"
depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
depends on ARCH_MULTI_V5
depends on !ARCH_SPEAR13XX
select ARM_VIC
help
@ -88,7 +87,7 @@ config MACH_SPEAR600
Supports ST SPEAr600 boards configured via the device-tree
config ARCH_SPEAR_AUTO
def_bool PLAT_SPEAR_SINGLE
bool
depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
select ARCH_SPEAR3XX

2
arch/arm/mach-vt8500/vt8500.c
View File

@ -69,7 +69,7 @@ static void vt8500_power_off(void)
{
local_irq_disable();
writew(5, pmc_base + VT8500_HCR_REG);
asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0));
}
static void __init vt8500_init(void)

2
drivers/ata/Kconfig
View File

@ -299,7 +299,7 @@ config SATA_HIGHBANK
config SATA_MV
tristate "Marvell SATA support"
depends on PCI || ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
depends on PCI || ARCH_DOVE || ARCH_MV78XX0 || \
ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST
select GENERIC_PHY
help

4
drivers/cpufreq/Kconfig.arm
View File

@ -77,7 +77,7 @@ config ARM_EXYNOS5440_CPUFREQ
config ARM_EXYNOS_CPU_FREQ_BOOST_SW
bool "EXYNOS Frequency Overclocking - Software"
depends on ARM_EXYNOS_CPUFREQ
depends on ARM_EXYNOS_CPUFREQ && THERMAL
select CPU_FREQ_BOOST_SW
select EXYNOS_THERMAL
help
@ -119,7 +119,7 @@ config ARM_INTEGRATOR
If in doubt, say Y.
config ARM_KIRKWOOD_CPUFREQ
def_bool ARCH_KIRKWOOD || MACH_KIRKWOOD
def_bool MACH_KIRKWOOD
help
This adds the CPUFreq driver for Marvell Kirkwood
SoCs.

2
drivers/cpuidle/Kconfig.arm
View File

@ -28,7 +28,7 @@ config ARM_HIGHBANK_CPUIDLE
config ARM_KIRKWOOD_CPUIDLE
bool "CPU Idle Driver for Marvell Kirkwood SoCs"
depends on ARCH_KIRKWOOD || MACH_KIRKWOOD
depends on MACH_KIRKWOOD
help
This adds the CPU Idle driver for Marvell Kirkwood SoCs.

4
drivers/leds/Kconfig
View File

@ -410,7 +410,7 @@ config LEDS_MC13783
config LEDS_NS2
tristate "LED support for Network Space v2 GPIO LEDs"
depends on LEDS_CLASS
depends on ARCH_KIRKWOOD || MACH_KIRKWOOD
depends on MACH_KIRKWOOD
default y
help
This option enable support for the dual-GPIO LED found on the
@ -420,7 +420,7 @@ config LEDS_NS2
config LEDS_NETXBIG
tristate "LED support for Big Network series LEDs"
depends on LEDS_CLASS
depends on ARCH_KIRKWOOD || MACH_KIRKWOOD
depends on MACH_KIRKWOOD
default y
help
This option enable support for LEDs found on the LaCie 2Big

2
drivers/rtc/Kconfig
View File

@ -1198,7 +1198,7 @@ config RTC_DRV_TX4939
config RTC_DRV_MV
tristate "Marvell SoC RTC"
depends on ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU
depends on ARCH_DOVE || ARCH_MVEBU
help
If you say yes here you will get support for the in-chip RTC
that can be found in some of Marvell's SoC devices, such as

2
drivers/thermal/Kconfig
View File

@ -143,7 +143,7 @@ config RCAR_THERMAL
config KIRKWOOD_THERMAL
tristate "Temperature sensor on Marvell Kirkwood SoCs"
depends on ARCH_KIRKWOOD || MACH_KIRKWOOD
depends on MACH_KIRKWOOD
depends on OF
help
Support for the Kirkwood thermal sensor driver into the Linux thermal

2
drivers/watchdog/Kconfig
View File

@ -301,7 +301,7 @@ config DAVINCI_WATCHDOG
config ORION_WATCHDOG
tristate "Orion watchdog"
depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU
depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer