forked from Minki/linux
drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wells
The dependency between power wells is determined by the ordering of the power well list: when enabling the power wells for a domain, this happens walking the power well list forward, while disabling them happens in the reverse direction. Accordingly a power well on the list must follow any other power well it depends on. Since the TC AUX power wells depend on TC-cold being blocked, move the TC-cold off power well before all AUX power wells. Fixes:3c02934b24
("drm/i915/tc/tgl: Implement TC cold sequences") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200720232952.16228-1-imre.deak@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (cherry picked from commitb302a2e688
) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -4146,6 +4146,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
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.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
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},
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},
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{
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.name = "TC cold off",
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.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
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.ops = &tgl_tc_cold_off_ops,
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.id = DISP_PW_ID_NONE,
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},
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{
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.name = "AUX A",
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.domains = TGL_AUX_A_IO_POWER_DOMAINS,
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@ -4332,12 +4338,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
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.hsw.irq_pipe_mask = BIT(PIPE_D),
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},
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},
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{
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.name = "TC cold off",
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.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
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.ops = &tgl_tc_cold_off_ops,
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.id = DISP_PW_ID_NONE,
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},
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};
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static const struct i915_power_well_desc rkl_power_wells[] = {
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