Arm SMMU updates for 5.7
- Support for the TLB range invalidation command in SMMUv3.2 - Introduction of command batching helpers... - ... which are then used to batch up CD and ATC invalidation - Support for PCI PASID, along with necessary PCI symbol exports - MAINTAINERS update to include DT binding docs -----BEGIN PGP SIGNATURE----- iQFEBAABCgAuFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAl50lY8QHHdpbGxAa2Vy bmVsLm9yZwAKCRC3rHDchMFjNOsjB/9ulzTxNbV53HSPWg22XgetOc7iO/6AfPyL q/DbRSyJK+EM6Fn3bKuoeDsC5YHVqp15lsOnOItePKyw/897w8bb9nopPI69lQLb EC4wBGIdL6PkkQ9dx/cXYK6p1OCNFD4Il+uTrwjxdx72fQyWrKi2+37kyZNifwQP 3vDCpIWLYYfGM8seD9Rvcz39XATaWPKLkPNI9nCuP4nMoZeGUvIqr/PYvEpxBpTv hTW4DAkSBvfiHOdH/Ecf160tINBdwiuMimfTtPuo2opXJGf9ZIf4baD3XoLzo2ta eLDO+9NOA25QrFPcyTThAHroHo2H24yyjrTyYamedQ/Rh8pSGJp0 =nBgf -----END PGP SIGNATURE----- Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu Arm SMMU updates for 5.7 - Support for the TLB range invalidation command in SMMUv3.2 - Introduction of command batching helpers... - ... which are then used to batch up CD and ATC invalidation - Support for PCI PASID, along with necessary PCI symbol exports - MAINTAINERS update to include DT binding docs
This commit is contained in:
Joerg Roedel
commit
49b6ed1ac8
@ -1426,6 +1426,7 @@ M: Will Deacon <will@kernel.org>
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R: Robin Murphy <robin.murphy@arm.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/iommu/arm,smmu*
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F: drivers/iommu/arm-smmu*
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F: drivers/iommu/io-pgtable-arm.c
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F: drivers/iommu/io-pgtable-arm-v7s.c
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@ -69,6 +69,9 @@
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#define IDR1_SSIDSIZE GENMASK(10, 6)
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#define IDR1_SIDSIZE GENMASK(5, 0)
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#define ARM_SMMU_IDR3 0xc
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#define IDR3_RIL (1 << 10)
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#define ARM_SMMU_IDR5 0x14
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#define IDR5_STALL_MAX GENMASK(31, 16)
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#define IDR5_GRAN64K (1 << 6)
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@ -346,9 +349,14 @@
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#define CMDQ_CFGI_1_LEAF (1UL << 0)
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#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)
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#define CMDQ_TLBI_0_NUM GENMASK_ULL(16, 12)
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#define CMDQ_TLBI_RANGE_NUM_MAX 31
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#define CMDQ_TLBI_0_SCALE GENMASK_ULL(24, 20)
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#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)
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#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)
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#define CMDQ_TLBI_1_LEAF (1UL << 0)
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#define CMDQ_TLBI_1_TTL GENMASK_ULL(9, 8)
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#define CMDQ_TLBI_1_TG GENMASK_ULL(11, 10)
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#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
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#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
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@ -473,9 +481,13 @@ struct arm_smmu_cmdq_ent {
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#define CMDQ_OP_TLBI_S2_IPA 0x2a
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#define CMDQ_OP_TLBI_NSNH_ALL 0x30
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struct {
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u8 num;
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u8 scale;
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u16 asid;
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u16 vmid;
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bool leaf;
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u8 ttl;
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u8 tg;
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u64 addr;
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} tlbi;
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@ -548,6 +560,11 @@ struct arm_smmu_cmdq {
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atomic_t lock;
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};
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struct arm_smmu_cmdq_batch {
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u64 cmds[CMDQ_BATCH_ENTRIES * CMDQ_ENT_DWORDS];
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int num;
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};
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struct arm_smmu_evtq {
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struct arm_smmu_queue q;
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u32 max_stalls;
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@ -627,6 +644,7 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_HYP (1 << 12)
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#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13)
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#define ARM_SMMU_FEAT_VAX (1 << 14)
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#define ARM_SMMU_FEAT_RANGE_INV (1 << 15)
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u32 features;
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#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
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@ -895,14 +913,22 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
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cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);
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break;
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case CMDQ_OP_TLBI_NH_VA:
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);
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cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
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break;
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case CMDQ_OP_TLBI_S2_IPA:
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);
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cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);
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cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);
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cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
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break;
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case CMDQ_OP_TLBI_NH_ASID:
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@ -1482,6 +1508,24 @@ static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu)
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return arm_smmu_cmdq_issue_cmdlist(smmu, NULL, 0, true);
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}
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static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,
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struct arm_smmu_cmdq_batch *cmds,
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struct arm_smmu_cmdq_ent *cmd)
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{
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if (cmds->num == CMDQ_BATCH_ENTRIES) {
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arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false);
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cmds->num = 0;
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}
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arm_smmu_cmdq_build_cmd(&cmds->cmds[cmds->num * CMDQ_ENT_DWORDS], cmd);
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cmds->num++;
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}
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static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,
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struct arm_smmu_cmdq_batch *cmds)
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{
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return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true);
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}
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/* Context descriptor manipulation functions */
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static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
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int ssid, bool leaf)
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@ -1489,6 +1533,7 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
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size_t i;
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unsigned long flags;
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struct arm_smmu_master *master;
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struct arm_smmu_cmdq_batch cmds = {};
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_cmdq_ent cmd = {
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.opcode = CMDQ_OP_CFGI_CD,
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@ -1502,12 +1547,12 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
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list_for_each_entry(master, &smmu_domain->devices, domain_head) {
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for (i = 0; i < master->num_sids; i++) {
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cmd.cfgi.sid = master->sids[i];
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arm_smmu_cmdq_issue_cmd(smmu, &cmd);
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arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);
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}
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}
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spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
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arm_smmu_cmdq_issue_sync(smmu);
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arm_smmu_cmdq_batch_submit(smmu, &cmds);
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}
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static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu,
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@ -1531,6 +1576,7 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst,
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u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) |
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CTXDESC_L1_DESC_V;
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/* See comment in arm_smmu_write_ctx_desc() */
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WRITE_ONCE(*dst, cpu_to_le64(val));
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}
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@ -1726,7 +1772,8 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
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val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span);
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val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
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*dst = cpu_to_le64(val);
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/* See comment in arm_smmu_write_ctx_desc() */
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WRITE_ONCE(*dst, cpu_to_le64(val));
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}
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static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
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@ -2132,17 +2179,16 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
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cmd->atc.size = log2_span;
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}
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static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,
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struct arm_smmu_cmdq_ent *cmd)
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static int arm_smmu_atc_inv_master(struct arm_smmu_master *master)
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{
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int i;
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struct arm_smmu_cmdq_ent cmd;
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if (!master->ats_enabled)
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return 0;
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arm_smmu_atc_inv_to_cmd(0, 0, 0, &cmd);
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for (i = 0; i < master->num_sids; i++) {
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cmd->atc.sid = master->sids[i];
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arm_smmu_cmdq_issue_cmd(master->smmu, cmd);
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cmd.atc.sid = master->sids[i];
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arm_smmu_cmdq_issue_cmd(master->smmu, &cmd);
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}
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return arm_smmu_cmdq_issue_sync(master->smmu);
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@ -2151,10 +2197,11 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,
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static int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain,
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int ssid, unsigned long iova, size_t size)
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{
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int ret = 0;
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int i;
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unsigned long flags;
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struct arm_smmu_cmdq_ent cmd;
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struct arm_smmu_master *master;
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struct arm_smmu_cmdq_batch cmds = {};
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if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS))
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return 0;
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@ -2179,11 +2226,18 @@ static int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain,
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arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd);
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spin_lock_irqsave(&smmu_domain->devices_lock, flags);
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list_for_each_entry(master, &smmu_domain->devices, domain_head)
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ret |= arm_smmu_atc_inv_master(master, &cmd);
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list_for_each_entry(master, &smmu_domain->devices, domain_head) {
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if (!master->ats_enabled)
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continue;
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for (i = 0; i < master->num_sids; i++) {
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cmd.atc.sid = master->sids[i];
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arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd);
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}
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}
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spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
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return ret ? -ETIMEDOUT : 0;
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return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds);
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}
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/* IO_PGTABLE API */
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@ -2218,10 +2272,10 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
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size_t granule, bool leaf,
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struct arm_smmu_domain *smmu_domain)
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{
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u64 cmds[CMDQ_BATCH_ENTRIES * CMDQ_ENT_DWORDS];
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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unsigned long start = iova, end = iova + size;
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int i = 0;
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unsigned long start = iova, end = iova + size, num_pages = 0, tg = 0;
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size_t inv_range = granule;
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struct arm_smmu_cmdq_batch cmds = {};
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struct arm_smmu_cmdq_ent cmd = {
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.tlbi = {
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.leaf = leaf,
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@ -2239,19 +2293,50 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
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cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
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}
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if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
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/* Get the leaf page size */
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tg = __ffs(smmu_domain->domain.pgsize_bitmap);
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/* Convert page size of 12,14,16 (log2) to 1,2,3 */
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cmd.tlbi.tg = (tg - 10) / 2;
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/* Determine what level the granule is at */
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cmd.tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3));
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num_pages = size >> tg;
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}
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while (iova < end) {
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if (i == CMDQ_BATCH_ENTRIES) {
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arm_smmu_cmdq_issue_cmdlist(smmu, cmds, i, false);
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i = 0;
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if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
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/*
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* On each iteration of the loop, the range is 5 bits
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* worth of the aligned size remaining.
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* The range in pages is:
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*
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* range = (num_pages & (0x1f << __ffs(num_pages)))
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*/
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unsigned long scale, num;
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/* Determine the power of 2 multiple number of pages */
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scale = __ffs(num_pages);
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cmd.tlbi.scale = scale;
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/* Determine how many chunks of 2^scale size we have */
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num = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX;
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cmd.tlbi.num = num - 1;
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/* range is num * 2^scale * pgsize */
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inv_range = num << (scale + tg);
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/* Clear out the lower order bits for the next iteration */
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num_pages -= num << scale;
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}
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cmd.tlbi.addr = iova;
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arm_smmu_cmdq_build_cmd(&cmds[i * CMDQ_ENT_DWORDS], &cmd);
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iova += granule;
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i++;
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arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);
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iova += inv_range;
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}
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arm_smmu_cmdq_issue_cmdlist(smmu, cmds, i, true);
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arm_smmu_cmdq_batch_submit(smmu, &cmds);
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/*
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* Unfortunately, this can't be leaf-only since we may have
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@ -2611,7 +2696,6 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master)
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static void arm_smmu_disable_ats(struct arm_smmu_master *master)
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{
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struct arm_smmu_cmdq_ent cmd;
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struct arm_smmu_domain *smmu_domain = master->domain;
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if (!master->ats_enabled)
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@ -2623,11 +2707,57 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master)
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* ATC invalidation via the SMMU.
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*/
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wmb();
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arm_smmu_atc_inv_to_cmd(0, 0, 0, &cmd);
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arm_smmu_atc_inv_master(master, &cmd);
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arm_smmu_atc_inv_master(master);
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atomic_dec(&smmu_domain->nr_ats_masters);
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}
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static int arm_smmu_enable_pasid(struct arm_smmu_master *master)
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{
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int ret;
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int features;
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int num_pasids;
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struct pci_dev *pdev;
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if (!dev_is_pci(master->dev))
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return -ENODEV;
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pdev = to_pci_dev(master->dev);
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features = pci_pasid_features(pdev);
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if (features < 0)
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return features;
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num_pasids = pci_max_pasids(pdev);
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if (num_pasids <= 0)
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return num_pasids;
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ret = pci_enable_pasid(pdev, features);
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if (ret) {
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dev_err(&pdev->dev, "Failed to enable PASID\n");
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return ret;
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}
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master->ssid_bits = min_t(u8, ilog2(num_pasids),
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master->smmu->ssid_bits);
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return 0;
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}
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static void arm_smmu_disable_pasid(struct arm_smmu_master *master)
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{
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struct pci_dev *pdev;
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if (!dev_is_pci(master->dev))
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return;
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pdev = to_pci_dev(master->dev);
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if (!pdev->pasid_enabled)
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return;
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master->ssid_bits = 0;
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pci_disable_pasid(pdev);
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}
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static void arm_smmu_detach_dev(struct arm_smmu_master *master)
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{
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unsigned long flags;
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@ -2831,13 +2961,23 @@ static int arm_smmu_add_device(struct device *dev)
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master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits);
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/*
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* Note that PASID must be enabled before, and disabled after ATS:
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* PCI Express Base 4.0r1.0 - 10.5.1.3 ATS Control Register
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*
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* Behavior is undefined if this bit is Set and the value of the PASID
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* Enable, Execute Requested Enable, or Privileged Mode Requested bits
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* are changed.
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*/
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arm_smmu_enable_pasid(master);
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|
||||
if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB))
|
||||
master->ssid_bits = min_t(u8, master->ssid_bits,
|
||||
CTXDESC_LINEAR_CDMAX);
|
||||
|
||||
ret = iommu_device_link(&smmu->iommu, dev);
|
||||
if (ret)
|
||||
goto err_free_master;
|
||||
goto err_disable_pasid;
|
||||
|
||||
group = iommu_group_get_for_dev(dev);
|
||||
if (IS_ERR(group)) {
|
||||
@ -2850,6 +2990,8 @@ static int arm_smmu_add_device(struct device *dev)
|
||||
|
||||
err_unlink:
|
||||
iommu_device_unlink(&smmu->iommu, dev);
|
||||
err_disable_pasid:
|
||||
arm_smmu_disable_pasid(master);
|
||||
err_free_master:
|
||||
kfree(master);
|
||||
fwspec->iommu_priv = NULL;
|
||||
@ -2870,6 +3012,7 @@ static void arm_smmu_remove_device(struct device *dev)
|
||||
arm_smmu_detach_dev(master);
|
||||
iommu_group_remove_device(dev);
|
||||
iommu_device_unlink(&smmu->iommu, dev);
|
||||
arm_smmu_disable_pasid(master);
|
||||
kfree(master);
|
||||
iommu_fwspec_free(dev);
|
||||
}
|
||||
@ -3700,6 +3843,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
|
||||
if (smmu->sid_bits <= STRTAB_SPLIT)
|
||||
smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;
|
||||
|
||||
/* IDR3 */
|
||||
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);
|
||||
if (FIELD_GET(IDR3_RIL, reg))
|
||||
smmu->features |= ARM_SMMU_FEAT_RANGE_INV;
|
||||
|
||||
/* IDR5 */
|
||||
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
|
||||
|
||||
|
||||
@ -366,6 +366,7 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_enable_pasid);
|
||||
|
||||
/**
|
||||
* pci_disable_pasid - Disable the PASID capability
|
||||
@ -390,6 +391,7 @@ void pci_disable_pasid(struct pci_dev *pdev)
|
||||
|
||||
pdev->pasid_enabled = 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_disable_pasid);
|
||||
|
||||
/**
|
||||
* pci_restore_pasid_state - Restore PASID capabilities
|
||||
@ -441,6 +443,7 @@ int pci_pasid_features(struct pci_dev *pdev)
|
||||
|
||||
return supported;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_pasid_features);
|
||||
|
||||
#define PASID_NUMBER_SHIFT 8
|
||||
#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
|
||||
@ -469,4 +472,5 @@ int pci_max_pasids(struct pci_dev *pdev)
|
||||
|
||||
return (1 << supported);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_max_pasids);
|
||||
#endif /* CONFIG_PCI_PASID */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user