drm/amdgpu: fix DW estimation on VI
Forgot to update that during recent changes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1628,7 +1628,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
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6 + /* sdma_v3_0_ring_emit_hdp_flush */
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3 + /* hdp invalidate */
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6 + /* sdma_v3_0_ring_emit_pipeline_sync */
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12 + /* sdma_v3_0_ring_emit_vm_flush */
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VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
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10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
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.emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
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.emit_ib = sdma_v3_0_ring_emit_ib,
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@ -1530,6 +1530,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
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.set_wptr = uvd_v6_0_ring_set_wptr,
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.parse_cs = amdgpu_uvd_ring_parse_cs,
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.emit_frame_size =
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6 + 6 + /* hdp flush / invalidate */
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10 + /* uvd_v6_0_ring_emit_pipeline_sync */
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14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
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.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
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@ -1541,6 +1542,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_uvd_ring_begin_use,
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.end_use = amdgpu_uvd_ring_end_use,
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.emit_wreg = uvd_v6_0_ring_emit_wreg,
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};
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static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
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@ -1554,7 +1556,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
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.emit_frame_size =
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6 + 6 + /* hdp flush / invalidate */
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10 + /* uvd_v6_0_ring_emit_pipeline_sync */
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20 + /* uvd_v6_0_ring_emit_vm_flush */
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VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
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14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
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.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
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.emit_ib = uvd_v6_0_ring_emit_ib,
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