forked from Minki/linux
dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180
The qcom,dispcc bindings had a few problems with them:
1. They didn't specify all the clocks that dispcc is a client of.
Specifically on sc7180 there are two clocks from the DSI PHY and
two from the DP PHY. On sdm845 there are actually two DSI PHYs
(each of which has two clocks) and an extra clock from the gcc.
These all need to be specified.
2. The sdm845.dtsi has existed for quite some time without specifying
the clocks. The Linux driver was relying on global names to match
things up. While we should transition things, it should be noted
in the bindings.
3. The names used the bindings for "xo" and "gpll0" didn't match the
names that QC used for these clocks internally and this was causing
confusion / difficulty with their code generation tools. Switched
to the internal names to simplify everyone's lives. It's not quite
as clean in a purist sense but it should avoid headaches. This
officially changes the binding, but that seems OK in this case.
Also note that I updated the example.
Fixes: 5d28e44ba6 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lkml.kernel.org/r/20200203103049.v4.2.I0c4bbb0f75a0880cd4bd90d8b267271e2375e0d0@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Douglas Anderson
Stephen Boyd
parent
908b050114
commit
48cabc221f
@ -1,67 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains.
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properties:
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compatible:
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enum:
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- qcom,sc7180-dispcc
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- qcom,sdm845-dispcc
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clocks:
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minItems: 1
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maxItems: 2
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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clock-names:
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items:
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- const: xo
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- const: gpll0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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examples:
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# Example of DISPCC with clock node properties for SDM845:
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- |
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clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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reg = <0xaf00000 0x10000>;
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clocks = <&rpmhcc 0>, <&gcc 24>;
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clock-names = "xo", "gpll0";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -0,0 +1,84 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SC7180
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SC7180.
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See also dt-bindings/clock/qcom,dispcc-sc7180.h.
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properties:
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compatible:
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const: qcom,sc7180-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk_src
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sc7180-dispcc";
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reg = <0 0x0af00000 0 0x200000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk_src",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -0,0 +1,99 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SDM845
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SDM845.
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See also dt-bindings/clock/qcom,dispcc-sdm845.h.
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properties:
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compatible:
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const: qcom,sdm845-dispcc
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# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
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# The code had to use hardcoded mechanisms to find the input clocks.
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# New dts files should have these clocks.
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: GPLL0 div source from GCC
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk_src
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- const: gcc_disp_gpll0_div_clk_src
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_byteclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_link_clk_divsel_ten
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- const: dp_vco_divided_clk_src_mux
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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reg = <0 0x0af00000 0 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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