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scsi: hisi_sas: Add support for interrupt converge for v3 hw

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If CQ_INT_CONVERGE_EN is enabled, the interrupts of all the 16 CQ queues
will be reported by CQ0.

So we need to change the process of CQ tasklet for this situation.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Xiang Chen 2018-11-09 22:06:33 +08:00 committed by Martin K. Petersen
parent c3566f9a61
commit 488cf558e3
1 changed files with 24 additions and 5 deletions
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29
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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@ -42,6 +42,7 @@
#define MAX_CON_TIME_LIMIT_TIME 0xa4 #define MAX_CON_TIME_LIMIT_TIME 0xa4
#define BUS_INACTIVE_LIMIT_TIME 0xa8 #define BUS_INACTIVE_LIMIT_TIME 0xa8
#define REJECT_TO_OPEN_LIMIT_TIME 0xac #define REJECT_TO_OPEN_LIMIT_TIME 0xac
#define CQ_INT_CONVERGE_EN 0xb0
#define CFG_AGING_TIME 0xbc #define CFG_AGING_TIME 0xbc
#define HGC_DFX_CFG2 0xc0 #define HGC_DFX_CFG2 0xc0
#define CFG_ABT_SET_QUERY_IPTT 0xd4 #define CFG_ABT_SET_QUERY_IPTT 0xd4
@ -371,6 +372,9 @@ struct hisi_sas_err_record_v3 {
((fis.command == ATA_CMD_DEV_RESET) && \ ((fis.command == ATA_CMD_DEV_RESET) && \
((fis.control & ATA_SRST) != 0))) ((fis.control & ATA_SRST) != 0)))
static bool hisi_sas_intr_conv;
MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{ {
void __iomem *regs = hisi_hba->regs + off; void __iomem *regs = hisi_hba->regs + off;
@ -436,6 +440,8 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
hisi_sas_intr_conv);
hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
@ -1880,10 +1886,12 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
for (i = 0; i < hisi_hba->queue_count; i++) { for (i = 0; i < hisi_hba->queue_count; i++) {
struct hisi_sas_cq *cq = &hisi_hba->cq[i]; struct hisi_sas_cq *cq = &hisi_hba->cq[i];
struct tasklet_struct *t = &cq->tasklet; struct tasklet_struct *t = &cq->tasklet;
int nr = hisi_sas_intr_conv ? 16 : 16 + i;
unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0;
rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), rc = devm_request_irq(dev, pci_irq_vector(pdev, nr),
cq_interrupt_v3_hw, 0, cq_interrupt_v3_hw, irqflags,
DRV_NAME " cq", cq); DRV_NAME " cq", cq);
if (rc) { if (rc) {
dev_err(dev, dev_err(dev,
"could not request cq%d interrupt, rc=%d\n", "could not request cq%d interrupt, rc=%d\n",
@ -1900,8 +1908,9 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
free_cq_irqs: free_cq_irqs:
for (k = 0; k < i; k++) { for (k = 0; k < i; k++) {
struct hisi_sas_cq *cq = &hisi_hba->cq[k]; struct hisi_sas_cq *cq = &hisi_hba->cq[k];
int nr = hisi_sas_intr_conv ? 16 : 16 + k;
free_irq(pci_irq_vector(pdev, k+16), cq); free_irq(pci_irq_vector(pdev, nr), cq);
} }
free_irq(pci_irq_vector(pdev, 11), hisi_hba); free_irq(pci_irq_vector(pdev, 11), hisi_hba);
free_chnl_interrupt: free_chnl_interrupt:
@ -2091,8 +2100,16 @@ static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
dev_dbg(dev, "wait commands complete %dms\n", time); dev_dbg(dev, "wait commands complete %dms\n", time);
} }
static ssize_t intr_conv_v3_hw_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
}
static DEVICE_ATTR_RO(intr_conv_v3_hw);
struct device_attribute *host_attrs_v3_hw[] = { struct device_attribute *host_attrs_v3_hw[] = {
&dev_attr_phy_event_threshold, &dev_attr_phy_event_threshold,
&dev_attr_intr_conv_v3_hw,
NULL NULL
}; };
@ -2305,8 +2322,9 @@ hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
free_irq(pci_irq_vector(pdev, 11), hisi_hba); free_irq(pci_irq_vector(pdev, 11), hisi_hba);
for (i = 0; i < hisi_hba->queue_count; i++) { for (i = 0; i < hisi_hba->queue_count; i++) {
struct hisi_sas_cq *cq = &hisi_hba->cq[i]; struct hisi_sas_cq *cq = &hisi_hba->cq[i];
int nr = hisi_sas_intr_conv ? 16 : 16 + i;
free_irq(pci_irq_vector(pdev, i+16), cq); free_irq(pci_irq_vector(pdev, nr), cq);
} }
pci_free_irq_vectors(pdev); pci_free_irq_vectors(pdev);
} }
@ -2628,6 +2646,7 @@ static struct pci_driver sas_v3_pci_driver = {
}; };
module_pci_driver(sas_v3_pci_driver); module_pci_driver(sas_v3_pci_driver);
module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); MODULE_AUTHOR("John Garry <john.garry@huawei.com>");