mmc: sdhci-tegra: Add comment for PADCALIB and PAD_CONTROL NVQUIRKS

This patch adds comments about NVQUIRKS HAS_PADCALIB and NEEDS_PAD_CONTROL.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1591326240-28928-1-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Sowjanya Komatineni 2020-06-04 20:04:00 -07:00 committed by Ulf Hansson
parent 557ed5f06c
commit 47fad46b7a

View File

@ -96,7 +96,16 @@
#define NVQUIRK_ENABLE_SDR50 BIT(3) #define NVQUIRK_ENABLE_SDR50 BIT(3)
#define NVQUIRK_ENABLE_SDR104 BIT(4) #define NVQUIRK_ENABLE_SDR104 BIT(4)
#define NVQUIRK_ENABLE_DDR50 BIT(5) #define NVQUIRK_ENABLE_DDR50 BIT(5)
/*
* HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
* drive strength.
*/
#define NVQUIRK_HAS_PADCALIB BIT(6) #define NVQUIRK_HAS_PADCALIB BIT(6)
/*
* NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
* 3V3/1V8 pad selection happens through pinctrl state selection depending
* on the signaling mode.
*/
#define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
#define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
#define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9)