staging: comedi: ni_pcidio: make defines uppercase
According to the Linux coding guidelines, defines should be written in uppercase. This patch converts all define-statements in the ni_pcidio.c file to uppercase, thus matching the coding style of the kernel. Signed-off-by: Alexander Schroth <alexander.schroth@fau.de> Signed-off-by: Marco Ammon <marco.ammon@fau.de> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Schroth
Greg Kroah-Hartman
parent
891fd84760
commit
47ed91d3a2
@ -49,116 +49,117 @@
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/* defines for the PCI-DIO-32HS */
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#define Window_Address 4 /* W */
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#define Interrupt_And_Window_Status 4 /* R */
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#define IntStatus1 BIT(0)
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#define IntStatus2 BIT(1)
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#define WindowAddressStatus_mask 0x7c
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#define WINDOW_ADDRESS 4 /* W */
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#define INTERRUPT_AND_WINDOW_STATUS 4 /* R */
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#define INT_STATUS_1 BIT(0)
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#define INT_STATUS_2 BIT(1)
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#define WINDOW_ADDRESS_STATUS_MASK 0x7c
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#define Master_DMA_And_Interrupt_Control 5 /* W */
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#define InterruptLine(x) ((x) & 3)
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#define OpenInt BIT(2)
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#define Group_Status 5 /* R */
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#define DataLeft BIT(0)
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#define Req BIT(2)
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#define StopTrig BIT(3)
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#define MASTER_DMA_AND_INTERRUPT_CONTROL 5 /* W */
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#define INTERRUPT_LINE(x) ((x) & 3)
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#define OPEN_INT BIT(2)
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#define GROUP_STATUS 5 /* R */
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#define DATA_LEFT BIT(0)
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#define REQ BIT(2)
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#define STOP_TRIG BIT(3)
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#define Group_1_Flags 6 /* R */
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#define Group_2_Flags 7 /* R */
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#define TransferReady BIT(0)
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#define CountExpired BIT(1)
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#define Waited BIT(5)
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#define PrimaryTC BIT(6)
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#define SecondaryTC BIT(7)
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#define GROUP_1_FLAGS 6 /* R */
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#define GROUP_2_FLAGS 7 /* R */
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#define TRANSFER_READY BIT(0)
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#define COUNT_EXPIRED BIT(1)
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#define WAITED BIT(5)
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#define PRIMARY_TC BIT(6)
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#define SECONDARY_TC BIT(7)
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/* #define SerialRose */
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/* #define ReqRose */
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/* #define Paused */
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#define Group_1_First_Clear 6 /* W */
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#define Group_2_First_Clear 7 /* W */
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#define ClearWaited BIT(3)
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#define ClearPrimaryTC BIT(4)
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#define ClearSecondaryTC BIT(5)
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#define DMAReset BIT(6)
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#define FIFOReset BIT(7)
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#define ClearAll 0xf8
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#define GROUP_1_FIRST_CLEAR 6 /* W */
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#define GROUP_2_FIRST_CLEAR 7 /* W */
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#define CLEAR_WAITED BIT(3)
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#define CLEAR_PRIMARY_TC BIT(4)
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#define CLEAR_SECONDARY_TC BIT(5)
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#define DMA_RESET BIT(6)
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#define FIFO_RESET BIT(7)
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#define CLEAR_ALL 0xf8
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#define Group_1_FIFO 8 /* W */
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#define Group_2_FIFO 12 /* W */
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#define GROUP_1_FIFO 8 /* W */
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#define GROUP_2_FIFO 12 /* W */
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#define Transfer_Count 20
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#define Chip_ID_D 24
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#define Chip_ID_I 25
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#define Chip_ID_O 26
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#define Chip_Version 27
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#define Port_IO(x) (28 + (x))
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#define Port_Pin_Directions(x) (32 + (x))
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#define Port_Pin_Mask(x) (36 + (x))
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#define Port_Pin_Polarities(x) (40 + (x))
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#define TRANSFER_COUNT 20
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#define CHIP_ID_D 24
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#define CHIP_ID_I 25
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#define CHIP_ID_O 26
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#define CHIP_VERSION 27
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#define PORT_IO(x) (28 + (x))
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#define PORT_PIN_DIRECTIONS(x) (32 + (x))
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#define PORT_PIN_MASK(x) (36 + (x))
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#define PORT_PIN_POLARITIES(x) (40 + (x))
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#define Master_Clock_Routing 45
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#define RTSIClocking(x) (((x) & 3) << 4)
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#define MASTER_CLOCK_ROUTING 45
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#define RTSI_CLOCKING(x) (((x) & 3) << 4)
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#define Group_1_Second_Clear 46 /* W */
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#define Group_2_Second_Clear 47 /* W */
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#define ClearExpired BIT(0)
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#define GROUP_1_SECOND_CLEAR 46 /* W */
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#define GROUP_2_SECOND_CLEAR 47 /* W */
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#define CLEAR_EXPIRED BIT(0)
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#define Port_Pattern(x) (48 + (x))
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#define PORT_PATTERN(x) (48 + (x))
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#define Data_Path 64
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#define FIFOEnableA BIT(0)
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#define FIFOEnableB BIT(1)
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#define FIFOEnableC BIT(2)
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#define FIFOEnableD BIT(3)
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#define Funneling(x) (((x) & 3) << 4)
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#define GroupDirection BIT(7)
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#define DATA_PATH 64
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#define FIFO_ENABLE_A BIT(0)
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#define FIFO_ENABLE_B BIT(1)
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#define FIFO_ENABLE_C BIT(2)
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#define FIFO_ENABLE_D BIT(3)
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#define FUNNELING(x) (((x) & 3) << 4)
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#define GROUP_DIRECTION BIT(7)
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#define Protocol_Register_1 65
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#define OpMode Protocol_Register_1
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#define RunMode(x) ((x) & 7)
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#define Numbered BIT(3)
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#define PROTOCOL_REGISTER_1 65
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#define OP_MODE PROTOCOL_REGISTER_1
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#define RUN_MODE(x) ((x) & 7)
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#define NUMBERED BIT(3)
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#define Protocol_Register_2 66
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#define ClockReg Protocol_Register_2
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#define ClockLine(x) (((x) & 3) << 5)
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#define InvertStopTrig BIT(7)
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#define DataLatching(x) (((x) & 3) << 5)
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#define PROTOCOL_REGISTER_2 66
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#define CLOCK_REG PROTOCOL_REGISTER_2
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#define CLOCK_LINE(x) (((x) & 3) << 5)
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#define INVERT_STOP_TRIG BIT(7)
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#define DATA_LATCHING(x) (((x) & 3) << 5)
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#define Protocol_Register_3 67
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#define Sequence Protocol_Register_3
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#define PROTOCOL_REGISTER_3 67
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#define SEQUENCE PROTOCOL_REGISTER_3
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#define Protocol_Register_14 68 /* 16 bit */
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#define ClockSpeed Protocol_Register_14
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#define PROTOCOL_REGISTER_14 68 /* 16 bit */
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#define CLOCK_SPEED PROTOCOL_REGISTER_14
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#define Protocol_Register_4 70
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#define ReqReg Protocol_Register_4
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#define ReqConditioning(x) (((x) & 7) << 3)
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#define PROTOCOL_REGISTER_4 70
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#define REQ_REG PROTOCOL_REGISTER_4
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#define REQ_CONDITIONING(x) (((x) & 7) << 3)
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#define Protocol_Register_5 71
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#define BlockMode Protocol_Register_5
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#define PROTOCOL_REGISTER_5 71
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#define BLOCK_MODE PROTOCOL_REGISTER_5
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#define FIFO_Control 72
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#define ReadyLevel(x) ((x) & 7)
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#define READY_LEVEL(x) ((x) & 7)
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#define Protocol_Register_6 73
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#define LinePolarities Protocol_Register_6
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#define InvertAck BIT(0)
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#define InvertReq BIT(1)
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#define InvertClock BIT(2)
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#define InvertSerial BIT(3)
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#define OpenAck BIT(4)
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#define OpenClock BIT(5)
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#define PROTOCOL_REGISTER_6 73
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#define LINE_POLARITIES PROTOCOL_REGISTER_6
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#define INVERT_ACK BIT(0)
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#define INVERT_REQ BIT(1)
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#define INVERT_CLOCK BIT(2)
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#define INVERT_SERIAL BIT(3)
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#define OPEN_ACK BIT(4)
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#define OPEN_CLOCK BIT(5)
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#define Protocol_Register_7 74
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#define AckSer Protocol_Register_7
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#define AckLine(x) (((x) & 3) << 2)
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#define ExchangePins BIT(7)
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#define PROTOCOL_REGISTER_7 74
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#define ACK_SER PROTOCOL_REGISTER_7
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#define ACK_LINE(x) (((x) & 3) << 2)
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#define EXCHANGE_PINS BIT(7)
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#define Interrupt_Control 75
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/* bits same as flags */
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#define INTERRUPT_CONTROL 75
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/* bits same as flags */
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#define DMA_LINE_CONTROL_GROUP1 76
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#define DMA_LINE_CONTROL_GROUP2 108
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#define DMA_Line_Control_Group1 76
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#define DMA_Line_Control_Group2 108
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/* channel zero is none */
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static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
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{
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@ -170,41 +171,41 @@ static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
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return (channel << 2) & 0xc;
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}
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#define Transfer_Size_Control 77
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#define TransferWidth(x) ((x) & 3)
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#define TransferLength(x) (((x) & 3) << 3)
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#define RequireRLevel BIT(5)
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#define TRANSFER_SIZE_CONTROL 77
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#define TRANSFER_WIDTH(x) ((x) & 3)
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#define TRANSFER_LENGTH(x) (((x) & 3) << 3)
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#define REQUIRE_R_LEVEL BIT(5)
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#define Protocol_Register_15 79
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#define DAQOptions Protocol_Register_15
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#define StartSource(x) ((x) & 0x3)
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#define InvertStart BIT(2)
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#define StopSource(x) (((x) & 0x3) << 3)
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#define ReqStart BIT(6)
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#define PreStart BIT(7)
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#define PROTOCOL_REGISTER_15 79
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#define DAQ_OPTIONS PROTOCOL_REGISTER_15
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#define START_SOURCE(x) ((x) & 0x3)
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#define INVERT_START BIT(2)
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#define STOP_SOURCE(x) (((x) & 0x3) << 3)
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#define REQ_START BIT(6)
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#define PRE_START BIT(7)
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#define Pattern_Detection 81
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#define DetectionMethod BIT(0)
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#define InvertMatch BIT(1)
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#define IE_Pattern_Detection BIT(2)
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#define PATTERN_DETECTION 81
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#define DETECTION_METHOD BIT(0)
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#define INVERT_MATCH BIT(1)
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#define IE_PATTERN_DETECTION BIT(2)
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#define Protocol_Register_9 82
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#define ReqDelay Protocol_Register_9
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#define PROTOCOL_REGISTER_9 82
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#define REQ_DELAY PROTOCOL_REGISTER_9
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#define Protocol_Register_10 83
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#define ReqNotDelay Protocol_Register_10
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#define PROTOCOL_REGISTER_10 83
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#define REQ_NOT_DELAY PROTOCOL_REGISTER_10
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#define Protocol_Register_11 84
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#define AckDelay Protocol_Register_11
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#define PROTOCOL_REGISTER_11 84
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#define ACK_DELAY PROTOCOL_REGISTER_11
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#define Protocol_Register_12 85
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#define AckNotDelay Protocol_Register_12
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#define PROTOCOL_REGISTER_12 85
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#define ACK_NOT_DELAY PROTOCOL_REGISTER_12
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#define Protocol_Register_13 86
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#define Data1Delay Protocol_Register_13
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#define PROTOCOL_REGISTER_13 86
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#define DATA_1_DELAY PROTOCOL_REGISTER_13
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#define Protocol_Register_8 88 /* 32 bit */
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#define StartDelay Protocol_Register_8
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#define PROTOCOL_REGISTER_8 88 /* 32 bit */
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#define START_DELAY PROTOCOL_REGISTER_8
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/* Firmware files for PCI-6524 */
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#define FW_PCI_6534_MAIN "ni6534a.bin"
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@ -246,9 +247,10 @@ enum FPGA_Control_Bits {
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#define TIMER_BASE 50 /* nanoseconds */
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#ifdef USE_DMA
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#define IntEn (CountExpired | Waited | PrimaryTC | SecondaryTC)
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#define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC)
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#else
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#define IntEn (TransferReady | CountExpired | Waited | PrimaryTC | SecondaryTC)
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#define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \
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| PRIMARY_TC | SECONDARY_TC)
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#endif
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enum nidio_boardid {
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@ -283,7 +285,7 @@ struct nidio96_private {
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struct mite *mite;
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int boardtype;
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int dio;
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unsigned short OpModeBits;
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unsigned short OP_MODEBits;
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struct mite_channel *di_mite_chan;
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struct mite_ring *di_mite_ring;
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spinlock_t mite_channel_lock;
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@ -307,7 +309,7 @@ static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
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devpriv->di_mite_chan->dir = COMEDI_INPUT;
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writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
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secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
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dev->mmio + DMA_Line_Control_Group1);
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dev->mmio + DMA_LINE_CONTROL_GROUP1);
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mmiowb();
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spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
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return 0;
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@ -324,7 +326,7 @@ static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
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devpriv->di_mite_chan = NULL;
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writeb(primary_DMAChannel_bits(0) |
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secondary_DMAChannel_bits(0),
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dev->mmio + DMA_Line_Control_Group1);
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dev->mmio + DMA_LINE_CONTROL_GROUP1);
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mmiowb();
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}
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spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
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@ -391,8 +393,8 @@ static irqreturn_t nidio_interrupt(int irq, void *d)
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/* Lock to avoid race with comedi_poll */
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spin_lock(&dev->spinlock);
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status = readb(dev->mmio + Interrupt_And_Window_Status);
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flags = readb(dev->mmio + Group_1_Flags);
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status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
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flags = readb(dev->mmio + GROUP_1_FLAGS);
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spin_lock(&devpriv->mite_channel_lock);
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if (devpriv->di_mite_chan) {
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@ -401,63 +403,63 @@ static irqreturn_t nidio_interrupt(int irq, void *d)
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}
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spin_unlock(&devpriv->mite_channel_lock);
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while (status & DataLeft) {
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while (status & DATA_LEFT) {
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work++;
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if (work > 20) {
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dev_dbg(dev->class_dev, "too much work in interrupt\n");
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writeb(0x00,
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dev->mmio + Master_DMA_And_Interrupt_Control);
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dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
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break;
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}
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flags &= IntEn;
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flags &= INT_EN;
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if (flags & TransferReady) {
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while (flags & TransferReady) {
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if (flags & TRANSFER_READY) {
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while (flags & TRANSFER_READY) {
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work++;
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if (work > 100) {
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dev_dbg(dev->class_dev,
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"too much work in interrupt\n");
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writeb(0x00, dev->mmio +
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Master_DMA_And_Interrupt_Control
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MASTER_DMA_AND_INTERRUPT_CONTROL
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);
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goto out;
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}
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auxdata = readl(dev->mmio + Group_1_FIFO);
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auxdata = readl(dev->mmio + GROUP_1_FIFO);
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comedi_buf_write_samples(s, &auxdata, 1);
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flags = readb(dev->mmio + Group_1_Flags);
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flags = readb(dev->mmio + GROUP_1_FLAGS);
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}
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}
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if (flags & CountExpired) {
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writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
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if (flags & COUNT_EXPIRED) {
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writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
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async->events |= COMEDI_CB_EOA;
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writeb(0x00, dev->mmio + OpMode);
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writeb(0x00, dev->mmio + OP_MODE);
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break;
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} else if (flags & Waited) {
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writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
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} else if (flags & WAITED) {
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writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
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async->events |= COMEDI_CB_ERROR;
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break;
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} else if (flags & PrimaryTC) {
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writeb(ClearPrimaryTC,
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dev->mmio + Group_1_First_Clear);
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} else if (flags & PRIMARY_TC) {
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writeb(CLEAR_PRIMARY_TC,
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dev->mmio + GROUP_1_FIRST_CLEAR);
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async->events |= COMEDI_CB_EOA;
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} else if (flags & SecondaryTC) {
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writeb(ClearSecondaryTC,
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dev->mmio + Group_1_First_Clear);
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} else if (flags & SECONDARY_TC) {
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writeb(CLEAR_SECONDARY_TC,
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dev->mmio + GROUP_1_FIRST_CLEAR);
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async->events |= COMEDI_CB_EOA;
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}
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flags = readb(dev->mmio + Group_1_Flags);
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status = readb(dev->mmio + Interrupt_And_Window_Status);
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flags = readb(dev->mmio + GROUP_1_FLAGS);
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status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
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}
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out:
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comedi_handle_events(dev, s);
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#if 0
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if (!tag)
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writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
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writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
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#endif
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spin_unlock(&dev->spinlock);
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@ -484,7 +486,7 @@ static int ni_pcidio_insn_config(struct comedi_device *dev,
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if (ret)
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return ret;
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writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
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writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
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return insn->n;
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}
|
||||
@ -495,9 +497,9 @@ static int ni_pcidio_insn_bits(struct comedi_device *dev,
|
||||
unsigned int *data)
|
||||
{
|
||||
if (comedi_dio_update_state(s, data))
|
||||
writel(s->state, dev->mmio + Port_IO(0));
|
||||
writel(s->state, dev->mmio + PORT_IO(0));
|
||||
|
||||
data[1] = readl(dev->mmio + Port_IO(0));
|
||||
data[1] = readl(dev->mmio + PORT_IO(0));
|
||||
|
||||
return insn->n;
|
||||
}
|
||||
@ -609,7 +611,7 @@ static int ni_pcidio_inttrig(struct comedi_device *dev,
|
||||
if (trig_num != cmd->start_arg)
|
||||
return -EINVAL;
|
||||
|
||||
writeb(devpriv->OpModeBits, dev->mmio + OpMode);
|
||||
writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
|
||||
s->async->inttrig = NULL;
|
||||
|
||||
return 1;
|
||||
@ -621,78 +623,78 @@ static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
struct comedi_cmd *cmd = &s->async->cmd;
|
||||
|
||||
/* XXX configure ports for input */
|
||||
writel(0x0000, dev->mmio + Port_Pin_Directions(0));
|
||||
writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
|
||||
|
||||
if (1) {
|
||||
/* enable fifos A B C D */
|
||||
writeb(0x0f, dev->mmio + Data_Path);
|
||||
writeb(0x0f, dev->mmio + DATA_PATH);
|
||||
|
||||
/* set transfer width a 32 bits */
|
||||
writeb(TransferWidth(0) | TransferLength(0),
|
||||
dev->mmio + Transfer_Size_Control);
|
||||
writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),
|
||||
dev->mmio + TRANSFER_SIZE_CONTROL);
|
||||
} else {
|
||||
writeb(0x03, dev->mmio + Data_Path);
|
||||
writeb(TransferWidth(3) | TransferLength(0),
|
||||
dev->mmio + Transfer_Size_Control);
|
||||
writeb(0x03, dev->mmio + DATA_PATH);
|
||||
writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),
|
||||
dev->mmio + TRANSFER_SIZE_CONTROL);
|
||||
}
|
||||
|
||||
/* protocol configuration */
|
||||
if (cmd->scan_begin_src == TRIG_TIMER) {
|
||||
/* page 4-5, "input with internal REQs" */
|
||||
writeb(0, dev->mmio + OpMode);
|
||||
writeb(0x00, dev->mmio + ClockReg);
|
||||
writeb(1, dev->mmio + Sequence);
|
||||
writeb(0x04, dev->mmio + ReqReg);
|
||||
writeb(4, dev->mmio + BlockMode);
|
||||
writeb(3, dev->mmio + LinePolarities);
|
||||
writeb(0xc0, dev->mmio + AckSer);
|
||||
writeb(0, dev->mmio + OP_MODE);
|
||||
writeb(0x00, dev->mmio + CLOCK_REG);
|
||||
writeb(1, dev->mmio + SEQUENCE);
|
||||
writeb(0x04, dev->mmio + REQ_REG);
|
||||
writeb(4, dev->mmio + BLOCK_MODE);
|
||||
writeb(3, dev->mmio + LINE_POLARITIES);
|
||||
writeb(0xc0, dev->mmio + ACK_SER);
|
||||
writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
|
||||
CMDF_ROUND_NEAREST),
|
||||
dev->mmio + StartDelay);
|
||||
writeb(1, dev->mmio + ReqDelay);
|
||||
writeb(1, dev->mmio + ReqNotDelay);
|
||||
writeb(1, dev->mmio + AckDelay);
|
||||
writeb(0x0b, dev->mmio + AckNotDelay);
|
||||
writeb(0x01, dev->mmio + Data1Delay);
|
||||
dev->mmio + START_DELAY);
|
||||
writeb(1, dev->mmio + REQ_DELAY);
|
||||
writeb(1, dev->mmio + REQ_NOT_DELAY);
|
||||
writeb(1, dev->mmio + ACK_DELAY);
|
||||
writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
|
||||
writeb(0x01, dev->mmio + DATA_1_DELAY);
|
||||
/*
|
||||
* manual, page 4-5:
|
||||
* ClockSpeed comment is incorrectly listed on DAQOptions
|
||||
* CLOCK_SPEED comment is incorrectly listed on DAQ_OPTIONS
|
||||
*/
|
||||
writew(0, dev->mmio + ClockSpeed);
|
||||
writeb(0, dev->mmio + DAQOptions);
|
||||
writew(0, dev->mmio + CLOCK_SPEED);
|
||||
writeb(0, dev->mmio + DAQ_OPTIONS);
|
||||
} else {
|
||||
/* TRIG_EXT */
|
||||
/* page 4-5, "input with external REQs" */
|
||||
writeb(0, dev->mmio + OpMode);
|
||||
writeb(0x00, dev->mmio + ClockReg);
|
||||
writeb(0, dev->mmio + Sequence);
|
||||
writeb(0x00, dev->mmio + ReqReg);
|
||||
writeb(4, dev->mmio + BlockMode);
|
||||
writeb(0, dev->mmio + OP_MODE);
|
||||
writeb(0x00, dev->mmio + CLOCK_REG);
|
||||
writeb(0, dev->mmio + SEQUENCE);
|
||||
writeb(0x00, dev->mmio + REQ_REG);
|
||||
writeb(4, dev->mmio + BLOCK_MODE);
|
||||
if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
|
||||
writeb(0, dev->mmio + LinePolarities);
|
||||
writeb(0, dev->mmio + LINE_POLARITIES);
|
||||
else /* Trailing Edge */
|
||||
writeb(2, dev->mmio + LinePolarities);
|
||||
writeb(0x00, dev->mmio + AckSer);
|
||||
writel(1, dev->mmio + StartDelay);
|
||||
writeb(1, dev->mmio + ReqDelay);
|
||||
writeb(1, dev->mmio + ReqNotDelay);
|
||||
writeb(1, dev->mmio + AckDelay);
|
||||
writeb(0x0C, dev->mmio + AckNotDelay);
|
||||
writeb(0x10, dev->mmio + Data1Delay);
|
||||
writew(0, dev->mmio + ClockSpeed);
|
||||
writeb(0x60, dev->mmio + DAQOptions);
|
||||
writeb(2, dev->mmio + LINE_POLARITIES);
|
||||
writeb(0x00, dev->mmio + ACK_SER);
|
||||
writel(1, dev->mmio + START_DELAY);
|
||||
writeb(1, dev->mmio + REQ_DELAY);
|
||||
writeb(1, dev->mmio + REQ_NOT_DELAY);
|
||||
writeb(1, dev->mmio + ACK_DELAY);
|
||||
writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
|
||||
writeb(0x10, dev->mmio + DATA_1_DELAY);
|
||||
writew(0, dev->mmio + CLOCK_SPEED);
|
||||
writeb(0x60, dev->mmio + DAQ_OPTIONS);
|
||||
}
|
||||
|
||||
if (cmd->stop_src == TRIG_COUNT) {
|
||||
writel(cmd->stop_arg,
|
||||
dev->mmio + Transfer_Count);
|
||||
dev->mmio + TRANSFER_COUNT);
|
||||
} else {
|
||||
/* XXX */
|
||||
}
|
||||
|
||||
#ifdef USE_DMA
|
||||
writeb(ClearPrimaryTC | ClearSecondaryTC,
|
||||
dev->mmio + Group_1_First_Clear);
|
||||
writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,
|
||||
dev->mmio + GROUP_1_FIRST_CLEAR);
|
||||
|
||||
{
|
||||
int retval = setup_mite_dma(dev, s);
|
||||
@ -701,25 +703,25 @@ static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
return retval;
|
||||
}
|
||||
#else
|
||||
writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
|
||||
writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
|
||||
#endif
|
||||
writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
|
||||
writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
|
||||
|
||||
/* clear and enable interrupts */
|
||||
writeb(0xff, dev->mmio + Group_1_First_Clear);
|
||||
/* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
|
||||
writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
|
||||
/* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
|
||||
|
||||
writeb(IntEn, dev->mmio + Interrupt_Control);
|
||||
writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
|
||||
writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
|
||||
writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
|
||||
|
||||
if (cmd->stop_src == TRIG_NONE) {
|
||||
devpriv->OpModeBits = DataLatching(0) | RunMode(7);
|
||||
devpriv->OP_MODEBits = DATA_LATCHING(0) | RUN_MODE(7);
|
||||
} else { /* TRIG_TIMER */
|
||||
devpriv->OpModeBits = Numbered | RunMode(7);
|
||||
devpriv->OP_MODEBits = NUMBERED | RUN_MODE(7);
|
||||
}
|
||||
if (cmd->start_src == TRIG_NOW) {
|
||||
/* start */
|
||||
writeb(devpriv->OpModeBits, dev->mmio + OpMode);
|
||||
writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
|
||||
s->async->inttrig = NULL;
|
||||
} else {
|
||||
/* TRIG_INT */
|
||||
@ -732,7 +734,7 @@ static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
static int ni_pcidio_cancel(struct comedi_device *dev,
|
||||
struct comedi_subdevice *s)
|
||||
{
|
||||
writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
|
||||
writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
|
||||
ni_pcidio_release_di_mite_channel(dev);
|
||||
|
||||
return 0;
|
||||
@ -869,12 +871,12 @@ static int pci_6534_upload_firmware(struct comedi_device *dev)
|
||||
|
||||
static void nidio_reset_board(struct comedi_device *dev)
|
||||
{
|
||||
writel(0, dev->mmio + Port_IO(0));
|
||||
writel(0, dev->mmio + Port_Pin_Directions(0));
|
||||
writel(0, dev->mmio + Port_Pin_Mask(0));
|
||||
writel(0, dev->mmio + PORT_IO(0));
|
||||
writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
|
||||
writel(0, dev->mmio + PORT_PIN_MASK(0));
|
||||
|
||||
/* disable interrupts on board */
|
||||
writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
|
||||
writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
|
||||
}
|
||||
|
||||
static int nidio_auto_attach(struct comedi_device *dev,
|
||||
@ -925,7 +927,7 @@ static int nidio_auto_attach(struct comedi_device *dev,
|
||||
return ret;
|
||||
|
||||
dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
|
||||
readb(dev->mmio + Chip_Version));
|
||||
readb(dev->mmio + CHIP_VERSION));
|
||||
|
||||
s = &dev->subdevices[0];
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user