forked from Minki/linux
KVM: x86: fix handling of role.cr4_pae and rename it to 'gpte_size'
The cr4_pae flag is a bit of a misnomer, its purpose is really to track
whether the guest PTE that is being shadowed is a 4-byte entry or an
8-byte entry. Prior to supporting nested EPT, the size of the gpte was
reflected purely by CR4.PAE. KVM fudged things a bit for direct sptes,
but it was mostly harmless since the size of the gpte never mattered.
Now that a spte may be tracking an indirect EPT entry, relying on
CR4.PAE is wrong and ill-named.
For direct shadow pages, force the gpte_size to '1' as they are always
8-byte entries; EPT entries can only be 8-bytes and KVM always uses
8-byte entries for NPT and its identity map (when running with EPT but
not unrestricted guest).
Likewise, nested EPT entries are always 8-bytes. Nested EPT presents a
unique scenario as the size of the entries are not dictated by CR4.PAE,
but neither is the shadow page a direct map. To handle this scenario,
set cr0_wp=1 and smap_andnot_wp=1, an otherwise impossible combination,
to denote a nested EPT shadow page. Use the information to avoid
incorrectly zapping an unsync'd indirect page in __kvm_sync_page().
Providing a consistent and accurate gpte_size fixes a bug reported by
Vitaly where fast_cr3_switch() always fails when switching from L2 to
L1 as kvm_mmu_get_page() would force role.cr4_pae=0 for direct pages,
whereas kvm_calc_mmu_role_common() would set it according to CR4.PAE.
Fixes: 7dcd575520
("x86/kvm/mmu: check if tdp/shadow MMU reconfiguration is needed")
Reported-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Tested-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
552c69b1dc
commit
47c42e6b41
@ -142,7 +142,7 @@ Shadow pages contain the following information:
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If clear, this page corresponds to a guest page table denoted by the gfn
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field.
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role.quadrant:
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When role.cr4_pae=0, the guest uses 32-bit gptes while the host uses 64-bit
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When role.gpte_is_8_bytes=0, the guest uses 32-bit gptes while the host uses 64-bit
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sptes. That means a guest page table contains more ptes than the host,
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so multiple shadow pages are needed to shadow one guest page.
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For first-level shadow pages, role.quadrant can be 0 or 1 and denotes the
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@ -158,9 +158,9 @@ Shadow pages contain the following information:
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The page is invalid and should not be used. It is a root page that is
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currently pinned (by a cpu hardware register pointing to it); once it is
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unpinned it will be destroyed.
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role.cr4_pae:
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Contains the value of cr4.pae for which the page is valid (e.g. whether
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32-bit or 64-bit gptes are in use).
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role.gpte_is_8_bytes:
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Reflects the size of the guest PTE for which the page is valid, i.e. '1'
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if 64-bit gptes are in use, '0' if 32-bit gptes are in use.
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role.nxe:
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Contains the value of efer.nxe for which the page is valid.
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role.cr0_wp:
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@ -173,6 +173,9 @@ Shadow pages contain the following information:
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Contains the value of cr4.smap && !cr0.wp for which the page is valid
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(pages for which this is true are different from other pages; see the
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treatment of cr0.wp=0 below).
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role.ept_sp:
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This is a virtual flag to denote a shadowed nested EPT page. ept_sp
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is true if "cr0_wp && smap_andnot_wp", an otherwise invalid combination.
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role.smm:
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Is 1 if the page is valid in system management mode. This field
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determines which of the kvm_memslots array was used to build this
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@ -253,14 +253,14 @@ struct kvm_mmu_memory_cache {
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* kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used
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* by indirect shadow page can not be more than 15 bits.
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*
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* Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access,
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* Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access,
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* @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp.
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*/
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union kvm_mmu_page_role {
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u32 word;
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struct {
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unsigned level:4;
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unsigned cr4_pae:1;
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unsigned gpte_is_8_bytes:1;
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unsigned quadrant:2;
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unsigned direct:1;
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unsigned access:3;
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@ -182,7 +182,7 @@ struct kvm_shadow_walk_iterator {
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static const union kvm_mmu_page_role mmu_base_role_mask = {
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.cr0_wp = 1,
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.cr4_pae = 1,
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.gpte_is_8_bytes = 1,
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.nxe = 1,
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.smep_andnot_wp = 1,
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.smap_andnot_wp = 1,
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@ -2205,6 +2205,7 @@ static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
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static void kvm_mmu_commit_zap_page(struct kvm *kvm,
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struct list_head *invalid_list);
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#define for_each_valid_sp(_kvm, _sp, _gfn) \
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hlist_for_each_entry(_sp, \
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&(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
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@ -2215,12 +2216,17 @@ static void kvm_mmu_commit_zap_page(struct kvm *kvm,
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for_each_valid_sp(_kvm, _sp, _gfn) \
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if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
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static inline bool is_ept_sp(struct kvm_mmu_page *sp)
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{
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return sp->role.cr0_wp && sp->role.smap_andnot_wp;
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}
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/* @sp->gfn should be write-protected at the call site */
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static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
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struct list_head *invalid_list)
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{
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if (sp->role.cr4_pae != !!is_pae(vcpu)
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|| vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
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if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
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vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
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kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
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return false;
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}
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@ -2423,7 +2429,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
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role.level = level;
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role.direct = direct;
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if (role.direct)
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role.cr4_pae = 0;
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role.gpte_is_8_bytes = true;
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role.access = access;
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if (!vcpu->arch.mmu->direct_map
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&& vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
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@ -4794,7 +4800,6 @@ static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
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role.base.access = ACC_ALL;
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role.base.nxe = !!is_nx(vcpu);
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role.base.cr4_pae = !!is_pae(vcpu);
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role.base.cr0_wp = is_write_protection(vcpu);
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role.base.smm = is_smm(vcpu);
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role.base.guest_mode = is_guest_mode(vcpu);
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@ -4815,6 +4820,7 @@ kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
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role.base.ad_disabled = (shadow_accessed_mask == 0);
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role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
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role.base.direct = true;
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role.base.gpte_is_8_bytes = true;
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return role;
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}
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@ -4879,6 +4885,7 @@ kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
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role.base.smap_andnot_wp = role.ext.cr4_smap &&
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!is_write_protection(vcpu);
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role.base.direct = !is_paging(vcpu);
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role.base.gpte_is_8_bytes = !!is_pae(vcpu);
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if (!is_long_mode(vcpu))
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role.base.level = PT32E_ROOT_LEVEL;
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@ -4919,21 +4926,24 @@ kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
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bool execonly)
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{
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union kvm_mmu_role role = {0};
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union kvm_mmu_page_role root_base = vcpu->arch.root_mmu.mmu_role.base;
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/* Legacy paging and SMM flags are inherited from root_mmu */
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role.base.smm = root_base.smm;
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role.base.nxe = root_base.nxe;
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role.base.cr0_wp = root_base.cr0_wp;
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role.base.smep_andnot_wp = root_base.smep_andnot_wp;
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role.base.smap_andnot_wp = root_base.smap_andnot_wp;
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/* SMM flag is inherited from root_mmu */
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role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
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role.base.level = PT64_ROOT_4LEVEL;
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role.base.gpte_is_8_bytes = true;
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role.base.direct = false;
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role.base.ad_disabled = !accessed_dirty;
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role.base.guest_mode = true;
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role.base.access = ACC_ALL;
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/*
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* WP=1 and NOT_WP=1 is an impossible combination, use WP and the
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* SMAP variation to denote shadow EPT entries.
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*/
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role.base.cr0_wp = true;
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role.base.smap_andnot_wp = true;
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role.ext = kvm_calc_mmu_role_ext(vcpu);
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role.ext.execonly = execonly;
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@ -5184,7 +5194,7 @@ static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
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gpa, bytes, sp->role.word);
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offset = offset_in_page(gpa);
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pte_size = sp->role.cr4_pae ? 8 : 4;
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pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
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/*
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* Sometimes, the OS only writes the last one bytes to update status
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@ -5208,7 +5218,7 @@ static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
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page_offset = offset_in_page(gpa);
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level = sp->role.level;
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*nspte = 1;
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if (!sp->role.cr4_pae) {
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if (!sp->role.gpte_is_8_bytes) {
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page_offset <<= 1; /* 32->64 */
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/*
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* A 32-bit pde maps 4MB while the shadow pdes map
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@ -29,10 +29,10 @@
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\
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role.word = __entry->role; \
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\
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trace_seq_printf(p, "sp gfn %llx l%u%s q%u%s %s%s" \
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trace_seq_printf(p, "sp gfn %llx l%u %u-byte q%u%s %s%s" \
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" %snxe %sad root %u %s%c", \
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__entry->gfn, role.level, \
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role.cr4_pae ? " pae" : "", \
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role.gpte_is_8_bytes ? 8 : 4, \
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role.quadrant, \
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role.direct ? " direct" : "", \
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access_str[role.access], \
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