drm/amd/powerplay: drop unnecessary Navi1x specific APIs
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
5a52694c75
commit
46a301e14e
@ -1376,59 +1376,6 @@ static int navi10_display_config_changed(struct smu_context *smu)
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return ret;
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}
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static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
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{
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int ret = 0, i = 0;
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uint32_t min_freq, max_freq, force_freq;
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enum smu_clk_type clk_type;
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enum smu_clk_type clks[] = {
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SMU_GFXCLK,
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SMU_MCLK,
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SMU_SOCCLK,
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};
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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clk_type = clks[i];
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ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
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if (ret)
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return ret;
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force_freq = highest ? max_freq : min_freq;
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
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if (ret)
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return ret;
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}
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return ret;
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}
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static int navi10_unforce_dpm_levels(struct smu_context *smu)
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{
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int ret = 0, i = 0;
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uint32_t min_freq, max_freq;
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enum smu_clk_type clk_type;
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enum smu_clk_type clks[] = {
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SMU_GFXCLK,
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SMU_MCLK,
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SMU_SOCCLK,
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};
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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clk_type = clks[i];
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ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
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if (ret)
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return ret;
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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return ret;
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}
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return ret;
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}
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static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
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{
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if (!value)
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@ -1681,47 +1628,6 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
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return ret;
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}
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static int navi10_get_profiling_clk_mask(struct smu_context *smu,
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enum amd_dpm_forced_level level,
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uint32_t *sclk_mask,
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uint32_t *mclk_mask,
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uint32_t *soc_mask)
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{
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int ret = 0;
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uint32_t level_count = 0;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
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if (sclk_mask)
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*sclk_mask = 0;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
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if (mclk_mask)
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*mclk_mask = 0;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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if(sclk_mask) {
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ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK, &level_count);
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if (ret)
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return ret;
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*sclk_mask = level_count - 1;
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}
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if(mclk_mask) {
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ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK, &level_count);
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if (ret)
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return ret;
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*mclk_mask = level_count - 1;
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}
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if(soc_mask) {
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ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
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if (ret)
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return ret;
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*soc_mask = level_count - 1;
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}
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}
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return ret;
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}
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static int navi10_notify_smc_display_config(struct smu_context *smu)
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{
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struct smu_clocks min_clocks = {0};
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@ -1954,155 +1860,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
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return 0;
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}
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static int navi10_set_performance_level(struct smu_context *smu,
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enum amd_dpm_forced_level level);
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static int navi10_set_standard_performance_level(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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uint32_t sclk_freq = 0, uclk_freq = 0;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
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uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
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break;
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case CHIP_NAVI14:
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sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
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uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
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break;
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default:
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/* by default, this is same as auto performance level */
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return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
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}
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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return ret;
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}
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static int navi10_set_peak_performance_level(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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uint32_t sclk_freq = 0, uclk_freq = 0;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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switch (adev->pdev->revision) {
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case 0xf0: /* XTX */
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case 0xc0:
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sclk_freq = NAVI10_PEAK_SCLK_XTX;
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break;
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case 0xf1: /* XT */
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case 0xc1:
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sclk_freq = NAVI10_PEAK_SCLK_XT;
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break;
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default: /* XL */
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sclk_freq = NAVI10_PEAK_SCLK_XL;
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break;
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}
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break;
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case CHIP_NAVI14:
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switch (adev->pdev->revision) {
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case 0xc7: /* XT */
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case 0xf4:
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sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
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break;
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case 0xc1: /* XTM */
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case 0xf2:
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sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
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break;
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case 0xc3: /* XLM */
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case 0xf3:
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sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
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break;
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case 0xc5: /* XTX */
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case 0xf6:
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sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
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break;
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default: /* XL */
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sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
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break;
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}
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break;
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case CHIP_NAVI12:
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sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
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break;
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default:
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ret = smu_v11_0_get_dpm_level_range(smu,
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SMU_SCLK,
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NULL,
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&sclk_freq);
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if (ret)
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return ret;
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}
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ret = smu_v11_0_get_dpm_level_range(smu,
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SMU_UCLK,
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NULL,
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&uclk_freq);
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if (ret)
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return ret;
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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return ret;
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}
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static int navi10_set_performance_level(struct smu_context *smu,
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enum amd_dpm_forced_level level)
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{
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int ret = 0;
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uint32_t sclk_mask, mclk_mask, soc_mask;
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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ret = smu_force_dpm_limit_value(smu, true);
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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ret = smu_force_dpm_limit_value(smu, false);
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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ret = smu_unforce_dpm_levels(smu);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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ret = navi10_set_standard_performance_level(smu);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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ret = smu_get_profiling_clk_mask(smu, level,
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&sclk_mask,
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&mclk_mask,
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&soc_mask);
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if (ret)
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return ret;
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smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
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smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
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smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = navi10_set_peak_performance_level(smu);
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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break;
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}
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return ret;
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}
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static int navi10_get_thermal_temperature_range(struct smu_context *smu,
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struct smu_temperature_range *range)
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{
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@ -2622,18 +2379,15 @@ static const struct pptable_funcs navi10_ppt_funcs = {
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.pre_display_config_changed = navi10_pre_display_config_changed,
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.display_config_changed = navi10_display_config_changed,
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.notify_smc_display_config = navi10_notify_smc_display_config,
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.force_dpm_limit_value = navi10_force_dpm_limit_value,
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.unforce_dpm_levels = navi10_unforce_dpm_levels,
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.is_dpm_running = navi10_is_dpm_running,
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.get_fan_speed_percent = navi10_get_fan_speed_percent,
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.get_fan_speed_rpm = navi10_get_fan_speed_rpm,
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.get_power_profile_mode = navi10_get_power_profile_mode,
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.set_power_profile_mode = navi10_set_power_profile_mode,
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.get_profiling_clk_mask = navi10_get_profiling_clk_mask,
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.set_watermarks_table = navi10_set_watermarks_table,
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.read_sensor = navi10_read_sensor,
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.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
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.set_performance_level = navi10_set_performance_level,
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.set_performance_level = smu_v11_0_set_performance_level,
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.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
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.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
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.get_power_limit = navi10_get_power_limit,
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