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drm/nv50/vm: remove explicit vm knowledge from engines

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This reverses the lock ordering between VM and gr/nv84:nvc0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2013-05-13 20:55:46 +10:00
parent c3032adb5c
commit 464d636bd0
9 changed files with 33 additions and 68 deletions
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8
drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
View File

@ -116,13 +116,6 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
nouveau_engctx_put(engctx);
}
static int
nva3_copy_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x0d);
return 0;
}
static int
nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
@ -142,7 +135,6 @@ nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->intr = nva3_copy_intr;
nv_engine(priv)->cclass = &nva3_copy_cclass;
nv_engine(priv)->sclass = nva3_copy_sclass;
nv_engine(priv)->tlb_flush = nva3_copy_tlb_flush;
nv_falcon(priv)->code.data = nva3_pcopy_code;
nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code);
nv_falcon(priv)->data.data = nva3_pcopy_data;

8
drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
View File

@ -140,13 +140,6 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
nouveau_engctx_put(engctx);
}
static int
nv84_crypt_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x0a);
return 0;
}
static int
nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
@ -165,7 +158,6 @@ nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->intr = nv84_crypt_intr;
nv_engine(priv)->cclass = &nv84_crypt_cclass;
nv_engine(priv)->sclass = nv84_crypt_sclass;
nv_engine(priv)->tlb_flush = nv84_crypt_tlb_flush;
return 0;
}

8
drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
View File

@ -118,13 +118,6 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
nouveau_engctx_put(engctx);
}
static int
nv98_crypt_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x0a);
return 0;
}
static int
nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
@ -143,7 +136,6 @@ nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->intr = nv98_crypt_intr;
nv_engine(priv)->cclass = &nv98_crypt_cclass;
nv_engine(priv)->sclass = nv98_crypt_sclass;
nv_engine(priv)->tlb_flush = nv98_crypt_tlb_flush;
nv_falcon(priv)->code.data = nv98_pcrypt_code;
nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
nv_falcon(priv)->data.data = nv98_pcrypt_data;

18
drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
View File

@ -186,13 +186,6 @@ nv50_graph_cclass = {
* PGRAPH engine/subdev functions
******************************************************************************/
static int
nv50_graph_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x00);
return 0;
}
static const struct nouveau_bitfield nv50_pgraph_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
@ -302,8 +295,10 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
nv_rd32(priv, 0x400388));
}
nv50_vm_flush_engine(&engine->base, 0x00);
nv_wr32(priv, 0x100c80, 0x00000001);
if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
nv_error(priv, "vm flush timeout\n");
nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
return timeout ? -EBUSY : 0;
@ -857,10 +852,9 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
};
if (nv_device(priv)->chipset == 0x50 ||
nv_device(priv)->chipset == 0xac)
nv_engine(priv)->tlb_flush = nv50_graph_tlb_flush;
else
/* unfortunate hw bug workaround... */
if (nv_device(priv)->chipset != 0x50 &&
nv_device(priv)->chipset != 0xac)
nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
spin_lock_init(&priv->lock);

8
drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
View File

@ -125,13 +125,6 @@ nv50_mpeg_cclass = {
* PMPEG engine/subdev functions
******************************************************************************/
int
nv50_mpeg_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x08);
return 0;
}
void
nv50_mpeg_intr(struct nouveau_subdev *subdev)
{
@ -191,7 +184,6 @@ nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->intr = nv50_vpe_intr;
nv_engine(priv)->cclass = &nv50_mpeg_cclass;
nv_engine(priv)->sclass = nv50_mpeg_sclass;
nv_engine(priv)->tlb_flush = nv50_mpeg_tlb_flush;
return 0;
}

1
drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
View File

@ -88,7 +88,6 @@ nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->intr = nv50_mpeg_intr;
nv_engine(priv)->cclass = &nv84_mpeg_cclass;
nv_engine(priv)->sclass = nv84_mpeg_sclass;
nv_engine(priv)->tlb_flush = nv50_mpeg_tlb_flush;
return 0;
}

1
drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
View File

@ -54,7 +54,6 @@ extern struct nouveau_ofuncs nv50_mpeg_ofuncs;
int nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
int nv50_mpeg_tlb_flush(struct nouveau_engine *);
void nv50_mpeg_intr(struct nouveau_subdev *);
int nv50_mpeg_init(struct nouveau_object *);

1
drivers/gpu/drm/nouveau/core/include/subdev/vm.h
View File

@ -117,7 +117,6 @@ int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64,
struct nouveau_vm **);
void nv04_vmmgr_dtor(struct nouveau_object *);
void nv50_vm_flush_engine(struct nouveau_subdev *, int engine);
void nvc0_vm_flush_engine(struct nouveau_subdev *, u64 addr, int type);
/* nouveau_vm.c */

48
drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
View File

@ -151,31 +151,37 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void
nv50_vm_flush(struct nouveau_vm *vm)
{
struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
struct nouveau_engine *engine;
int i;
for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
if (atomic_read(&vm->engref[i]) && i == NVDEV_SUBDEV_BAR) {
nv50_vm_flush_engine(nv_subdev(vm->vmm), 6);
} else
if (atomic_read(&vm->engref[i])) {
engine = nouveau_engine(vm->vmm, i);
if (engine && engine->tlb_flush)
engine->tlb_flush(engine);
}
}
}
void
nv50_vm_flush_engine(struct nouveau_subdev *subdev, int engine)
{
struct nv50_vmmgr_priv *priv = (void *)nouveau_vmmgr(subdev);
unsigned long flags;
int i, vme;
spin_lock_irqsave(&priv->lock, flags);
nv_wr32(subdev, 0x100c80, (engine << 16) | 1);
if (!nv_wait(subdev, 0x100c80, 0x00000001, 0x00000000))
nv_error(subdev, "vm flush timeout: engine %d\n", engine);
for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
if (!atomic_read(&vm->engref[i]))
continue;
/* unfortunate hw bug workaround... */
engine = nouveau_engine(priv, i);
if (engine && engine->tlb_flush) {
engine->tlb_flush(engine);
continue;
}
switch (i) {
case NVDEV_ENGINE_GR : vme = 0x00; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
default:
continue;
}
nv_wr32(priv, 0x100c80, (vme << 16) | 1);
if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
nv_error(priv, "vm flush timeout: engine %d\n", vme);
}
spin_unlock_irqrestore(&priv->lock, flags);
}