forked from Minki/linux
clk: sunxi: Add a driver for the PLL2
The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Maxime Ripard
parent
f2e0a53271
commit
460d0d4448
@ -4,6 +4,7 @@
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a10-pll2.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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188
drivers/clk/sunxi/clk-a10-pll2.c
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188
drivers/clk/sunxi/clk-a10-pll2.c
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@ -0,0 +1,188 @@
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/*
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* Copyright 2013 Emilio López
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* Emilio López <emilio@elopez.com.ar>
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*
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* Copyright 2015 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
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#define SUN4I_PLL2_ENABLE 31
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#define SUN4I_PLL2_PRE_DIV_SHIFT 0
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#define SUN4I_PLL2_PRE_DIV_WIDTH 5
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#define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
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#define SUN4I_PLL2_N_SHIFT 8
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#define SUN4I_PLL2_N_WIDTH 7
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#define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
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#define SUN4I_PLL2_POST_DIV_SHIFT 26
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#define SUN4I_PLL2_POST_DIV_WIDTH 4
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#define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
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#define SUN4I_PLL2_POST_DIV_VALUE 4
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#define SUN4I_PLL2_OUTPUTS 4
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static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
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static void __init sun4i_pll2_setup(struct device_node *node)
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{
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const char *clk_name = node->name, *parent;
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struct clk **clks, *base_clk, *prediv_clk;
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struct clk_onecell_data *clk_data;
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struct clk_multiplier *mult;
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struct clk_gate *gate;
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void __iomem *reg;
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u32 val;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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goto err_unmap;
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clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
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if (!clks)
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goto err_free_data;
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parent = of_clk_get_parent_name(node, 0);
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prediv_clk = clk_register_divider(NULL, "pll2-prediv",
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parent, 0, reg,
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SUN4I_PLL2_PRE_DIV_SHIFT,
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SUN4I_PLL2_PRE_DIV_WIDTH,
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CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO,
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&sun4i_a10_pll2_lock);
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if (!prediv_clk) {
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pr_err("Couldn't register the prediv clock\n");
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goto err_free_array;
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}
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/* Setup the gate part of the PLL2 */
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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goto err_unregister_prediv;
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gate->reg = reg;
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gate->bit_idx = SUN4I_PLL2_ENABLE;
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gate->lock = &sun4i_a10_pll2_lock;
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/* Setup the multiplier part of the PLL2 */
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mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
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if (!mult)
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goto err_free_gate;
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mult->reg = reg;
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mult->shift = SUN4I_PLL2_N_SHIFT;
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mult->width = 7;
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mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
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CLK_MULTIPLIER_ROUND_CLOSEST;
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mult->lock = &sun4i_a10_pll2_lock;
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parent = __clk_get_name(prediv_clk);
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base_clk = clk_register_composite(NULL, "pll2-base",
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&parent, 1,
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NULL, NULL,
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&mult->hw, &clk_multiplier_ops,
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&gate->hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (!base_clk) {
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pr_err("Couldn't register the base multiplier clock\n");
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goto err_free_multiplier;
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}
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parent = __clk_get_name(base_clk);
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/*
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* PLL2-1x
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*
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* This is supposed to have a post divider, but we won't need
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* to use it, we just need to initialise it to 4, and use a
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* fixed divider.
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*/
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val = readl(reg);
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val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
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val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT;
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writel(val, reg);
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of_property_read_string_index(node, "clock-output-names",
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SUN4I_A10_PLL2_1X, &clk_name);
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clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
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parent,
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CLK_SET_RATE_PARENT,
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1,
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SUN4I_PLL2_POST_DIV_VALUE);
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
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/*
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* PLL2-2x
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*
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* This clock doesn't use the post divider, and really is just
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* a fixed divider from the PLL2 base clock.
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*/
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of_property_read_string_index(node, "clock-output-names",
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SUN4I_A10_PLL2_2X, &clk_name);
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clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
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parent,
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CLK_SET_RATE_PARENT,
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1, 2);
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
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/* PLL2-4x */
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of_property_read_string_index(node, "clock-output-names",
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SUN4I_A10_PLL2_4X, &clk_name);
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clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
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parent,
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CLK_SET_RATE_PARENT,
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1, 1);
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
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/* PLL2-8x */
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of_property_read_string_index(node, "clock-output-names",
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SUN4I_A10_PLL2_8X, &clk_name);
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clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
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parent,
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CLK_SET_RATE_PARENT,
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2, 1);
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
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clk_data->clks = clks;
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clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return;
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err_free_multiplier:
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kfree(mult);
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err_free_gate:
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kfree(gate);
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err_unregister_prediv:
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clk_unregister_divider(prediv_clk);
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err_free_array:
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kfree(clks);
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err_free_data:
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kfree(clk_data);
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err_unmap:
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iounmap(reg);
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}
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CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup);
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53
include/dt-bindings/clock/sun4i-a10-pll2.h
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53
include/dt-bindings/clock/sun4i-a10-pll2.h
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@ -0,0 +1,53 @@
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/*
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
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#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
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#define SUN4I_A10_PLL2_1X 0
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#define SUN4I_A10_PLL2_2X 1
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#define SUN4I_A10_PLL2_4X 2
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#define SUN4I_A10_PLL2_8X 3
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#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
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