Merge branch 'fec-next'
Frank Li says: ==================== net: fec: imx6sx multiqueue support These patches enable i.MX6SX multi queue support. i.MX6SX support 3 queue and AVB feature. Change from v3 to v4 - use "unsigned int" instead of "unsigned" Change from v2 to v3 - fixed alignment requirement for ARM and NO-ARM platform Change from v1 to v2. - Change num_tx_queue to unsigned int - Avoid block non-dt platform - remove call netif_set_real_num_rx_queues - seperate multi queue patch two part, one is tx and rx handle, with fixed queue 0 then other one is initilized multiqueue - use two difference alignment for tx and rx path ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
45f85a2565
@ -16,6 +16,12 @@ Optional properties:
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- phy-handle : phandle to the PHY device connected to this device.
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- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
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Use instead of phy-handle.
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- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
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hw multi queues. Should specify the tx queue number, otherwise set tx queue
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number to 1.
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- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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hw multi queues. Should specify the rx queue number, otherwise set rx queue
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number to 1.
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Optional subnodes:
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- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
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@ -776,6 +776,8 @@
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<&clks IMX6SX_CLK_ENET_PTP>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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status = "disabled";
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};
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@ -27,8 +27,8 @@
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*/
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#define FEC_IEVENT 0x004 /* Interrupt event reg */
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#define FEC_IMASK 0x008 /* Interrupt mask reg */
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#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
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#define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
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#define FEC_ECNTRL 0x024 /* Ethernet control reg */
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#define FEC_MII_DATA 0x040 /* MII manage frame reg */
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#define FEC_MII_SPEED 0x044 /* MII speed control reg */
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@ -38,6 +38,12 @@
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#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
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#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
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#define FEC_OPD 0x0ec /* Opcode + Pause duration */
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#define FEC_TXIC0 0xF0 /* Tx Interrupt Coalescing for ring 0 */
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#define FEC_TXIC1 0xF4 /* Tx Interrupt Coalescing for ring 1 */
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#define FEC_TXIC2 0xF8 /* Tx Interrupt Coalescing for ring 2 */
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#define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
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#define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
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#define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
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#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
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#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
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#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
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@ -45,14 +51,27 @@
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#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
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#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
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#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
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#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
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#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
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#define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
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#define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
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#define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
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#define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
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#define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
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#define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
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#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
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#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
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#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
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#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
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#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
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#define FEC_RACC 0x1C4 /* Receive Accelerator function */
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#define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */
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#define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */
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#define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */
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#define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */
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#define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
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#define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
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#define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
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#define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
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#define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
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#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
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#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
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@ -233,6 +252,43 @@ struct bufdesc_ex {
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/* This device has up to three irqs on some platforms */
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#define FEC_IRQ_NUM 3
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/* Maximum number of queues supported
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* ENET with AVB IP can support up to 3 independent tx queues and rx queues.
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* User can point the queue number that is less than or equal to 3.
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*/
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#define FEC_ENET_MAX_TX_QS 3
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#define FEC_ENET_MAX_RX_QS 3
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#define FEC_R_DES_START(X) ((X == 1) ? FEC_R_DES_START_1 : \
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((X == 2) ? \
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FEC_R_DES_START_2 : FEC_R_DES_START_0))
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#define FEC_X_DES_START(X) ((X == 1) ? FEC_X_DES_START_1 : \
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((X == 2) ? \
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FEC_X_DES_START_2 : FEC_X_DES_START_0))
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#define FEC_R_DES_ACTIVE(X) ((X == 1) ? FEC_R_DES_ACTIVE_1 : \
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((X == 2) ? \
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FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0))
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#define FEC_X_DES_ACTIVE(X) ((X == 1) ? FEC_X_DES_ACTIVE_1 : \
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((X == 2) ? \
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FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0))
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#define FEC_DMA_CFG(X) ((X == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
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#define DMA_CLASS_EN (1 << 16)
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#define FEC_RCMR(X) ((X == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
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#define IDLE_SLOPE_MASK 0xFFFF
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#define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */
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#define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */
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#define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
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(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
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#define RCMR_MATCHEN (0x1 << 16)
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#define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2))
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#define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
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RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
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#define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
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RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
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#define RCMR_CMP(X) ((X == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
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/* The number of Tx and Rx buffers. These are allocated from the page
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* pool. The code may assume these are power of two, so it it best
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* to keep them that size.
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@ -256,6 +312,61 @@ struct bufdesc_ex {
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#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
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#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
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/* Interrupt events/masks. */
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#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
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#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
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#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
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#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
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#define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */
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#define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */
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#define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */
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#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
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#define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */
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#define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */
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#define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */
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#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
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#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
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#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
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#define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
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#define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
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#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
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#define FEC_ENET_TS_TIMER ((uint)0x00008000)
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#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
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#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
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#define FEC_VLAN_TAG_LEN 0x04
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#define FEC_ETHTYPE_LEN 0x02
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struct fec_enet_priv_tx_q {
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int index;
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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dma_addr_t bd_dma;
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struct bufdesc *tx_bd_base;
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uint tx_ring_size;
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unsigned short tx_stop_threshold;
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unsigned short tx_wake_threshold;
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struct bufdesc *cur_tx;
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struct bufdesc *dirty_tx;
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char *tso_hdrs;
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dma_addr_t tso_hdrs_dma;
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};
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struct fec_enet_priv_rx_q {
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int index;
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struct sk_buff *rx_skbuff[RX_RING_SIZE];
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dma_addr_t bd_dma;
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struct bufdesc *rx_bd_base;
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uint rx_ring_size;
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struct bufdesc *cur_rx;
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};
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/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
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* tx_bd_base always point to the base of the buffer descriptors. The
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* cur_rx and cur_tx point to the currently available buffer.
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@ -272,36 +383,28 @@ struct fec_enet_private {
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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struct clk *clk_ref;
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struct clk *clk_enet_out;
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struct clk *clk_ptp;
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bool ptp_clk_on;
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struct mutex ptp_clk_mutex;
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unsigned int num_tx_queues;
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unsigned int num_rx_queues;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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struct sk_buff *rx_skbuff[RX_RING_SIZE];
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struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
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struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
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/* CPM dual port RAM relative addresses */
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dma_addr_t bd_dma;
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/* Address of Rx and Tx buffers */
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struct bufdesc *rx_bd_base;
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struct bufdesc *tx_bd_base;
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/* The next free ring entry */
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struct bufdesc *cur_rx, *cur_tx;
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/* The ring entries to be free()ed */
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struct bufdesc *dirty_tx;
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unsigned int total_tx_ring_size;
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unsigned int total_rx_ring_size;
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unsigned long work_tx;
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unsigned long work_rx;
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unsigned long work_ts;
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unsigned long work_mdio;
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unsigned short bufdesc_size;
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unsigned short tx_ring_size;
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unsigned short rx_ring_size;
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unsigned short tx_stop_threshold;
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unsigned short tx_wake_threshold;
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/* Software TSO */
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char *tso_hdrs;
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dma_addr_t tso_hdrs_dma;
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struct platform_device *pdev;
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@ -340,6 +443,9 @@ struct fec_enet_private {
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int hwts_tx_en;
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struct delayed_work time_keep;
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struct regulator *reg_phy;
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unsigned int tx_align;
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unsigned int rx_align;
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};
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void fec_ptp_init(struct platform_device *pdev);
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