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MIPS: Malta: GIC IPIs may be used without MT

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It's perfectly valid to use SMP on a non-MT CPU and use the GIC for
IPIs. Set them up conditional upon CONFIG_MIPS_GIC_IPI rather than
CONFIG_MIPS_MT_SMP.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/6654/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
2014-03-24 10:19:32 +00:00
committed by Ralf Baechle
parent 0c2cb004b2
commit 45b2957804
1 changed files with 11 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/mips/mti-malta/malta-int.c
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@@ -286,10 +286,6 @@ asmlinkage void plat_irq_dispatch(void)
#ifdef CONFIG_MIPS_MT_SMP #ifdef CONFIG_MIPS_MT_SMP
#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
#define GIC_MIPS_CPU_IPI_CALL_IRQ 4
#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
#define C_RESCHED C_SW0 #define C_RESCHED C_SW0
#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
@@ -306,6 +302,13 @@ static void ipi_call_dispatch(void)
do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
} }
#endif /* CONFIG_MIPS_MT_SMP */
#ifdef CONFIG_MIPS_GIC_IPI
#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
#define GIC_MIPS_CPU_IPI_CALL_IRQ 4
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{ {
#ifdef MIPS_VPE_APSP_API #ifdef MIPS_VPE_APSP_API
@@ -336,7 +339,7 @@ static struct irqaction irq_call = {
.flags = IRQF_PERCPU, .flags = IRQF_PERCPU,
.name = "IPI_call" .name = "IPI_call"
}; };
#endif /* CONFIG_MIPS_MT_SMP */ #endif /* CONFIG_MIPS_GIC_IPI */
static int gic_resched_int_base; static int gic_resched_int_base;
static int gic_call_int_base; static int gic_call_int_base;
@@ -416,7 +419,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
}; };
#undef X #undef X
#if defined(CONFIG_MIPS_MT_SMP) #ifdef CONFIG_MIPS_GIC_IPI
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
{ {
int intr = baseintr + cpu; int intr = baseintr + cpu;
@@ -532,7 +535,7 @@ void __init arch_init_irq(void)
if (gic_present) { if (gic_present) {
/* FIXME */ /* FIXME */
int i; int i;
#if defined(CONFIG_MIPS_MT_SMP) #if defined(CONFIG_MIPS_GIC_IPI)
gic_call_int_base = GIC_NUM_INTRS - gic_call_int_base = GIC_NUM_INTRS -
(NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids; (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
gic_resched_int_base = gic_call_int_base - nr_cpu_ids; gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
@@ -547,7 +550,7 @@ void __init arch_init_irq(void)
(i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
pr_debug("GIC Enabled\n"); pr_debug("GIC Enabled\n");
} }
#if defined(CONFIG_MIPS_MT_SMP) #if defined(CONFIG_MIPS_GIC_IPI)
/* set up ipi interrupts */ /* set up ipi interrupts */
if (cpu_has_vint) { if (cpu_has_vint) {
set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);