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mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

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TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of IRQs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu IRQs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Kuppuswamy Sathyanarayanan 2017-06-05 12:08:01 -07:00 committed by Lee Jones
parent 2ea659a9ef
commit 4533d8551b
1 changed files with 4 additions and 1 deletions
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5
drivers/mfd/intel_soc_pmic_bxtwc.c
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@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
BXTWC_GPIO0_IRQ,
BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
BXTWC_TMU_IRQ,
};
enum bxtwc_irqs_tmu {
BXTWC_TMU_IRQ = 0,
};
static const struct regmap_irq bxtwc_regmap_irqs[] = {