forked from Minki/linux
drm/i915/chv: Tune L3 SQC credits based on actual latencies
While browsing BSpec I bumped into a note saying we need to tune these values based on actual measurements done after initial enabling. I've checked that it indeed improves things on BXT. I haven't checked this on CHV, but here it is if someone wants to give it a go. v2: - Add note about the discrepancy wrt. to the spec in the formula calculating the credit encodings. (Mika, Ville) - Move the WA comment to the new function. (Ville) v3: - Keep the comment about the SQC WA in the caller. (Ville) CC: Ville Syrjälä <ville.syrjala@linux.intel.com> CC: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-4-git-send-email-imre.deak@intel.com
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36579cb63b
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drivers/gpu/drm/i915
@ -6091,6 +6091,12 @@ enum skl_disp_power_wells {
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#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
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#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
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#define GEN8_L3SQCREG1 _MMIO(0xB100)
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#define GEN8_L3SQCREG1 _MMIO(0xB100)
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/*
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* Note that on CHV the following has an off-by-one error wrt. to BSpec.
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* Using the formula in BSpec leads to a hang, while the formula here works
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* fine and matches the formulas for all other platforms. A BSpec change
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* request has been filed to clarify this.
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*/
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#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
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#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
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#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
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#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
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@ -6696,11 +6696,33 @@ static void lpt_suspend_hw(struct drm_device *dev)
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}
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}
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}
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}
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static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
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int general_prio_credits,
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int high_prio_credits)
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{
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u32 misccpctl;
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/* WaTempDisableDOPClkGating:bdw */
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misccpctl = I915_READ(GEN7_MISCCPCTL);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
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I915_WRITE(GEN8_L3SQCREG1,
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L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
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L3_HIGH_PRIO_CREDITS(high_prio_credits));
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/*
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* Wait at least 100 clocks before re-enabling clock gating.
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* See the definition of L3SQCREG1 in BSpec.
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*/
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POSTING_READ(GEN8_L3SQCREG1);
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udelay(1);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl);
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}
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static void broadwell_init_clock_gating(struct drm_device *dev)
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static void broadwell_init_clock_gating(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe;
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enum pipe pipe;
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uint32_t misccpctl;
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ilk_init_lp_watermarks(dev);
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ilk_init_lp_watermarks(dev);
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@ -6731,21 +6753,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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/*
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/* WaProgramL3SqcReg1Default:bdw */
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* WaProgramL3SqcReg1Default:bdw
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gen8_set_l3sqc_credits(dev_priv, 30, 2);
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* WaTempDisableDOPClkGating:bdw
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*/
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misccpctl = I915_READ(GEN7_MISCCPCTL);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
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I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(30) |
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L3_HIGH_PRIO_CREDITS(2));
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/*
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* Wait at least 100 clocks before re-enabling clock gating. See
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* the definition of L3SQCREG1 in BSpec.
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*/
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POSTING_READ(GEN8_L3SQCREG1);
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udelay(1);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl);
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/*
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/*
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* WaGttCachingOffByDefault:bdw
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* WaGttCachingOffByDefault:bdw
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@ -7015,6 +7024,13 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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/*
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* WaProgramL3SqcReg1Default:chv
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* See gfxspecs/Related Documents/Performance Guide/
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* LSQC Setting Recommendations.
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*/
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gen8_set_l3sqc_credits(dev_priv, 38, 2);
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/*
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/*
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* GTT cache may not work with big pages, so if those
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* GTT cache may not work with big pages, so if those
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* are ever enabled GTT cache may need to be disabled.
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* are ever enabled GTT cache may need to be disabled.
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