RDMA/irdma: Implement device initialization definitions
Implement device initialization routines, interrupt set-up, and allocate object bit-map tracking structures. Also, add device specific attributes and register definitions. Link: https://lore.kernel.org/r/20210602205138.889-3-shiraz.saleem@intel.com [flexible array transformation] Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Mustafa Ismail
Jason Gunthorpe
parent
8498a30e1b
commit
44d9e52977
2725
drivers/infiniband/hw/irdma/hw.c
Normal file
2725
drivers/infiniband/hw/irdma/hw.c
Normal file
File diff suppressed because it is too large
Load Diff
216
drivers/infiniband/hw/irdma/i40iw_hw.c
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216
drivers/infiniband/hw/irdma/i40iw_hw.c
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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/* Copyright (c) 2015 - 2021 Intel Corporation */
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#include "osdep.h"
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#include "type.h"
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#include "i40iw_hw.h"
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#include "status.h"
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#include "protos.h"
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static u32 i40iw_regs[IRDMA_MAX_REGS] = {
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I40E_PFPE_CQPTAIL,
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I40E_PFPE_CQPDB,
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I40E_PFPE_CCQPSTATUS,
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I40E_PFPE_CCQPHIGH,
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I40E_PFPE_CCQPLOW,
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I40E_PFPE_CQARM,
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I40E_PFPE_CQACK,
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I40E_PFPE_AEQALLOC,
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I40E_PFPE_CQPERRCODES,
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I40E_PFPE_WQEALLOC,
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I40E_PFINT_DYN_CTLN(0),
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I40IW_DB_ADDR_OFFSET,
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I40E_GLPCI_LBARCTRL,
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I40E_GLPE_CPUSTATUS0,
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I40E_GLPE_CPUSTATUS1,
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I40E_GLPE_CPUSTATUS2,
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I40E_PFINT_AEQCTL,
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I40E_PFINT_CEQCTL(0),
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I40E_VSIQF_CTL(0),
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I40E_PFHMC_PDINV,
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I40E_GLHMC_VFPDINV(0),
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I40E_GLPE_CRITERR,
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0xffffffff /* PFINT_RATEN not used in FPK */
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};
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static u32 i40iw_stat_offsets_32[IRDMA_HW_STAT_INDEX_MAX_32] = {
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I40E_GLPES_PFIP4RXDISCARD(0),
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I40E_GLPES_PFIP4RXTRUNC(0),
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I40E_GLPES_PFIP4TXNOROUTE(0),
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I40E_GLPES_PFIP6RXDISCARD(0),
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I40E_GLPES_PFIP6RXTRUNC(0),
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I40E_GLPES_PFIP6TXNOROUTE(0),
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I40E_GLPES_PFTCPRTXSEG(0),
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I40E_GLPES_PFTCPRXOPTERR(0),
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I40E_GLPES_PFTCPRXPROTOERR(0),
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I40E_GLPES_PFRXVLANERR(0)
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};
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static u32 i40iw_stat_offsets_64[IRDMA_HW_STAT_INDEX_MAX_64] = {
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I40E_GLPES_PFIP4RXOCTSLO(0),
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I40E_GLPES_PFIP4RXPKTSLO(0),
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I40E_GLPES_PFIP4RXFRAGSLO(0),
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I40E_GLPES_PFIP4RXMCPKTSLO(0),
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I40E_GLPES_PFIP4TXOCTSLO(0),
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I40E_GLPES_PFIP4TXPKTSLO(0),
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I40E_GLPES_PFIP4TXFRAGSLO(0),
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I40E_GLPES_PFIP4TXMCPKTSLO(0),
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I40E_GLPES_PFIP6RXOCTSLO(0),
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I40E_GLPES_PFIP6RXPKTSLO(0),
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I40E_GLPES_PFIP6RXFRAGSLO(0),
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I40E_GLPES_PFIP6RXMCPKTSLO(0),
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I40E_GLPES_PFIP6TXOCTSLO(0),
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I40E_GLPES_PFIP6TXPKTSLO(0),
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I40E_GLPES_PFIP6TXFRAGSLO(0),
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I40E_GLPES_PFIP6TXMCPKTSLO(0),
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I40E_GLPES_PFTCPRXSEGSLO(0),
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I40E_GLPES_PFTCPTXSEGLO(0),
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I40E_GLPES_PFRDMARXRDSLO(0),
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I40E_GLPES_PFRDMARXSNDSLO(0),
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I40E_GLPES_PFRDMARXWRSLO(0),
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I40E_GLPES_PFRDMATXRDSLO(0),
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I40E_GLPES_PFRDMATXSNDSLO(0),
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I40E_GLPES_PFRDMATXWRSLO(0),
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I40E_GLPES_PFRDMAVBNDLO(0),
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I40E_GLPES_PFRDMAVINVLO(0),
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I40E_GLPES_PFIP4RXMCOCTSLO(0),
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I40E_GLPES_PFIP4TXMCOCTSLO(0),
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I40E_GLPES_PFIP6RXMCOCTSLO(0),
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I40E_GLPES_PFIP6TXMCOCTSLO(0),
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I40E_GLPES_PFUDPRXPKTSLO(0),
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I40E_GLPES_PFUDPTXPKTSLO(0)
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};
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static u64 i40iw_masks[IRDMA_MAX_MASKS] = {
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I40E_PFPE_CCQPSTATUS_CCQP_DONE,
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I40E_PFPE_CCQPSTATUS_CCQP_ERR,
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I40E_CQPSQ_STAG_PDID,
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I40E_CQPSQ_CQ_CEQID,
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I40E_CQPSQ_CQ_CQID,
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I40E_COMMIT_FPM_CQCNT,
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};
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static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = {
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I40E_PFPE_CCQPSTATUS_CCQP_DONE_S,
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I40E_PFPE_CCQPSTATUS_CCQP_ERR_S,
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I40E_CQPSQ_STAG_PDID_S,
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I40E_CQPSQ_CQ_CEQID_S,
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I40E_CQPSQ_CQ_CQID_S,
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I40E_COMMIT_FPM_CQCNT_S,
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};
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/**
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* i40iw_config_ceq- Configure CEQ interrupt
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* @dev: pointer to the device structure
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* @ceq_id: Completion Event Queue ID
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* @idx: vector index
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* @enable: Enable CEQ interrupt when true
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*/
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static void i40iw_config_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
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bool enable)
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{
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u32 reg_val;
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reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) |
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FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_TYPE, QUEUE_TYPE_CEQ);
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wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val);
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reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, 0x3) |
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FIELD_PREP(I40E_PFINT_DYN_CTLN_INTENA, 0x1);
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wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val);
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reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
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FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) |
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FIELD_PREP(I40E_PFINT_CEQCTL_NEXTQ_INDX, NULL_QUEUE_INDEX) |
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FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 0x3);
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wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val);
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}
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/**
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* i40iw_ena_irq - Enable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void i40iw_ena_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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u32 val;
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val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 0x1) |
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FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 0x1) |
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FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0x3);
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wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), val);
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}
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/**
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* i40iw_disable_irq - Disable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void i40iw_disable_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), 0);
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}
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static const struct irdma_irq_ops i40iw_irq_ops = {
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.irdma_cfg_aeq = irdma_cfg_aeq,
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.irdma_cfg_ceq = i40iw_config_ceq,
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.irdma_dis_irq = i40iw_disable_irq,
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.irdma_en_irq = i40iw_ena_irq,
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};
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void i40iw_init_hw(struct irdma_sc_dev *dev)
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{
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int i;
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u8 __iomem *hw_addr;
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for (i = 0; i < IRDMA_MAX_REGS; ++i) {
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hw_addr = dev->hw->hw_addr;
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if (i == IRDMA_DB_ADDR_OFFSET)
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hw_addr = NULL;
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dev->hw_regs[i] = (u32 __iomem *)(i40iw_regs[i] + hw_addr);
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}
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for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_32; ++i)
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dev->hw_stats_regs_32[i] = i40iw_stat_offsets_32[i];
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for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_64; ++i)
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dev->hw_stats_regs_64[i] = i40iw_stat_offsets_64[i];
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dev->hw_attrs.first_hw_vf_fpm_id = I40IW_FIRST_VF_FPM_ID;
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dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
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for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
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dev->hw_shifts[i] = i40iw_shifts[i];
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for (i = 0; i < IRDMA_MAX_MASKS; ++i)
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dev->hw_masks[i] = i40iw_masks[i];
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dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
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dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
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dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
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dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
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dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
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dev->ceq_itr_mask_db = NULL;
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dev->aeq_itr_mask_db = NULL;
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dev->irq_ops = &i40iw_irq_ops;
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/* Setup the hardware limits, hmc may limit further */
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dev->hw_attrs.uk_attrs.max_hw_wq_frags = I40IW_MAX_WQ_FRAGMENT_COUNT;
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dev->hw_attrs.uk_attrs.max_hw_read_sges = I40IW_MAX_SGE_RD;
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dev->hw_attrs.max_hw_device_pages = I40IW_MAX_PUSH_PAGE_COUNT;
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dev->hw_attrs.uk_attrs.max_hw_inline = I40IW_MAX_INLINE_DATA_SIZE;
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dev->hw_attrs.max_hw_ird = I40IW_MAX_IRD_SIZE;
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dev->hw_attrs.max_hw_ord = I40IW_MAX_ORD_SIZE;
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dev->hw_attrs.max_hw_wqes = I40IW_MAX_WQ_ENTRIES;
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dev->hw_attrs.uk_attrs.max_hw_rq_quanta = I40IW_QP_SW_MAX_RQ_QUANTA;
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dev->hw_attrs.uk_attrs.max_hw_wq_quanta = I40IW_QP_SW_MAX_WQ_QUANTA;
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dev->hw_attrs.uk_attrs.max_hw_sq_chunk = I40IW_MAX_QUANTA_PER_WR;
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dev->hw_attrs.max_hw_pds = I40IW_MAX_PDS;
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dev->hw_attrs.max_stat_inst = I40IW_MAX_STATS_COUNT;
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dev->hw_attrs.max_hw_outbound_msg_size = I40IW_MAX_OUTBOUND_MSG_SIZE;
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dev->hw_attrs.max_hw_inbound_msg_size = I40IW_MAX_INBOUND_MSG_SIZE;
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dev->hw_attrs.max_qp_wr = I40IW_MAX_QP_WRS;
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}
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160
drivers/infiniband/hw/irdma/i40iw_hw.h
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160
drivers/infiniband/hw/irdma/i40iw_hw.h
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/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
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/* Copyright (c) 2015 - 2021 Intel Corporation */
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#ifndef I40IW_HW_H
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#define I40IW_HW_H
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#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
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#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
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#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
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#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
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#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
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#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
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#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
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#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
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#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
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#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
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#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
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#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */
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#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */
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#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */
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#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
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#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
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#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */
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#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */
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#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
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#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */
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#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */
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#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
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#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */
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#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */
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#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */
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#define I40E_GLPE_CRITERR 0x000B4000 /* Reset: PE_CORER */
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#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
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#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
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#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
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#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
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#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
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#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
|
||||
|
||||
#define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024)
|
||||
|
||||
#define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
|
||||
|
||||
#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
|
||||
#define I40E_PFINT_LNKLSTN_MAX_INDEX 511
|
||||
#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0)
|
||||
#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE GENMASK(12, 11)
|
||||
|
||||
#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
|
||||
#define I40E_PFINT_CEQCTL_MAX_INDEX 511
|
||||
|
||||
/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
|
||||
#define I40E_PFINT_CEQCTL_MSIX_INDX_S 0
|
||||
#define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0)
|
||||
#define I40E_PFINT_CEQCTL_ITR_INDX_S 11
|
||||
#define I40E_PFINT_CEQCTL_ITR_INDX GENMASK(12, 11)
|
||||
#define I40E_PFINT_CEQCTL_MSIX0_INDX_S 13
|
||||
#define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13)
|
||||
#define I40E_PFINT_CEQCTL_NEXTQ_INDX_S 16
|
||||
#define I40E_PFINT_CEQCTL_NEXTQ_INDX GENMASK(26, 16)
|
||||
#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_S 27
|
||||
#define I40E_PFINT_CEQCTL_NEXTQ_TYPE GENMASK(28, 27)
|
||||
#define I40E_PFINT_CEQCTL_CAUSE_ENA_S 30
|
||||
#define I40E_PFINT_CEQCTL_CAUSE_ENA BIT(30)
|
||||
#define I40E_PFINT_CEQCTL_INTEVENT_S 31
|
||||
#define I40E_PFINT_CEQCTL_INTEVENT BIT(31)
|
||||
#define I40E_CQPSQ_STAG_PDID_S 48
|
||||
#define I40E_CQPSQ_STAG_PDID GENMASK_ULL(62, 48)
|
||||
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S 0
|
||||
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
|
||||
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_S 31
|
||||
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
|
||||
#define I40E_PFINT_DYN_CTLN_ITR_INDX_S 3
|
||||
#define I40E_PFINT_DYN_CTLN_ITR_INDX GENMASK(4, 3)
|
||||
#define I40E_PFINT_DYN_CTLN_INTENA_S 0
|
||||
#define I40E_PFINT_DYN_CTLN_INTENA BIT(0)
|
||||
#define I40E_CQPSQ_CQ_CEQID_S 24
|
||||
#define I40E_CQPSQ_CQ_CEQID GENMASK(30, 24)
|
||||
#define I40E_CQPSQ_CQ_CQID_S 0
|
||||
#define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)
|
||||
#define I40E_COMMIT_FPM_CQCNT_S 0
|
||||
#define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)
|
||||
|
||||
#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4))
|
||||
|
||||
enum i40iw_device_caps_const {
|
||||
I40IW_MAX_WQ_FRAGMENT_COUNT = 3,
|
||||
I40IW_MAX_SGE_RD = 1,
|
||||
I40IW_MAX_PUSH_PAGE_COUNT = 0,
|
||||
I40IW_MAX_INLINE_DATA_SIZE = 48,
|
||||
I40IW_MAX_IRD_SIZE = 63,
|
||||
I40IW_MAX_ORD_SIZE = 127,
|
||||
I40IW_MAX_WQ_ENTRIES = 2048,
|
||||
I40IW_MAX_WQE_SIZE_RQ = 128,
|
||||
I40IW_MAX_PDS = 32768,
|
||||
I40IW_MAX_STATS_COUNT = 16,
|
||||
I40IW_MAX_CQ_SIZE = 1048575,
|
||||
I40IW_MAX_OUTBOUND_MSG_SIZE = 2147483647,
|
||||
I40IW_MAX_INBOUND_MSG_SIZE = 2147483647,
|
||||
};
|
||||
|
||||
#define I40IW_QP_WQE_MIN_SIZE 32
|
||||
#define I40IW_QP_WQE_MAX_SIZE 128
|
||||
#define I40IW_QP_SW_MIN_WQSIZE 4
|
||||
#define I40IW_MAX_RQ_WQE_SHIFT 2
|
||||
#define I40IW_MAX_QUANTA_PER_WR 2
|
||||
|
||||
#define I40IW_QP_SW_MAX_SQ_QUANTA 2048
|
||||
#define I40IW_QP_SW_MAX_RQ_QUANTA 16384
|
||||
#define I40IW_QP_SW_MAX_WQ_QUANTA 2048
|
||||
#define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTA - IRDMA_SQ_RSVD) / I40IW_MAX_QUANTA_PER_WR)
|
||||
#define I40IW_FIRST_VF_FPM_ID 16
|
||||
#define QUEUE_TYPE_CEQ 2
|
||||
#define NULL_QUEUE_INDEX 0x7FF
|
||||
|
||||
void i40iw_init_hw(struct irdma_sc_dev *dev);
|
||||
#endif /* I40IW_HW_H */
|
||||
149
drivers/infiniband/hw/irdma/icrdma_hw.c
Normal file
149
drivers/infiniband/hw/irdma/icrdma_hw.c
Normal file
@ -0,0 +1,149 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
|
||||
/* Copyright (c) 2017 - 2021 Intel Corporation */
|
||||
#include "osdep.h"
|
||||
#include "type.h"
|
||||
#include "icrdma_hw.h"
|
||||
|
||||
static u32 icrdma_regs[IRDMA_MAX_REGS] = {
|
||||
PFPE_CQPTAIL,
|
||||
PFPE_CQPDB,
|
||||
PFPE_CCQPSTATUS,
|
||||
PFPE_CCQPHIGH,
|
||||
PFPE_CCQPLOW,
|
||||
PFPE_CQARM,
|
||||
PFPE_CQACK,
|
||||
PFPE_AEQALLOC,
|
||||
PFPE_CQPERRCODES,
|
||||
PFPE_WQEALLOC,
|
||||
GLINT_DYN_CTL(0),
|
||||
ICRDMA_DB_ADDR_OFFSET,
|
||||
|
||||
GLPCI_LBARCTRL,
|
||||
GLPE_CPUSTATUS0,
|
||||
GLPE_CPUSTATUS1,
|
||||
GLPE_CPUSTATUS2,
|
||||
PFINT_AEQCTL,
|
||||
GLINT_CEQCTL(0),
|
||||
VSIQF_PE_CTL1(0),
|
||||
PFHMC_PDINV,
|
||||
GLHMC_VFPDINV(0),
|
||||
GLPE_CRITERR,
|
||||
GLINT_RATE(0),
|
||||
};
|
||||
|
||||
static u64 icrdma_masks[IRDMA_MAX_MASKS] = {
|
||||
ICRDMA_CCQPSTATUS_CCQP_DONE,
|
||||
ICRDMA_CCQPSTATUS_CCQP_ERR,
|
||||
ICRDMA_CQPSQ_STAG_PDID,
|
||||
ICRDMA_CQPSQ_CQ_CEQID,
|
||||
ICRDMA_CQPSQ_CQ_CQID,
|
||||
ICRDMA_COMMIT_FPM_CQCNT,
|
||||
};
|
||||
|
||||
static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
|
||||
ICRDMA_CCQPSTATUS_CCQP_DONE_S,
|
||||
ICRDMA_CCQPSTATUS_CCQP_ERR_S,
|
||||
ICRDMA_CQPSQ_STAG_PDID_S,
|
||||
ICRDMA_CQPSQ_CQ_CEQID_S,
|
||||
ICRDMA_CQPSQ_CQ_CQID_S,
|
||||
ICRDMA_COMMIT_FPM_CQCNT_S,
|
||||
};
|
||||
|
||||
/**
|
||||
* icrdma_ena_irq - Enable interrupt
|
||||
* @dev: pointer to the device structure
|
||||
* @idx: vector index
|
||||
*/
|
||||
static void icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx)
|
||||
{
|
||||
u32 val;
|
||||
u32 interval = 0;
|
||||
|
||||
if (dev->ceq_itr && dev->aeq->msix_idx != idx)
|
||||
interval = dev->ceq_itr >> 1; /* 2 usec units */
|
||||
val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0) |
|
||||
FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTERVAL, interval) |
|
||||
FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 1) |
|
||||
FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 1);
|
||||
|
||||
if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
|
||||
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
|
||||
else
|
||||
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
|
||||
}
|
||||
|
||||
/**
|
||||
* icrdma_disable_irq - Disable interrupt
|
||||
* @dev: pointer to the device structure
|
||||
* @idx: vector index
|
||||
*/
|
||||
static void icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx)
|
||||
{
|
||||
if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
|
||||
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
|
||||
else
|
||||
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
|
||||
}
|
||||
|
||||
/**
|
||||
* icrdma_cfg_ceq- Configure CEQ interrupt
|
||||
* @dev: pointer to the device structure
|
||||
* @ceq_id: Completion Event Queue ID
|
||||
* @idx: vector index
|
||||
* @enable: True to enable, False disables
|
||||
*/
|
||||
static void icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
|
||||
bool enable)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
|
||||
FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) |
|
||||
FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 3);
|
||||
|
||||
writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
|
||||
}
|
||||
|
||||
static const struct irdma_irq_ops icrdma_irq_ops = {
|
||||
.irdma_cfg_aeq = irdma_cfg_aeq,
|
||||
.irdma_cfg_ceq = icrdma_cfg_ceq,
|
||||
.irdma_dis_irq = icrdma_disable_irq,
|
||||
.irdma_en_irq = icrdma_ena_irq,
|
||||
};
|
||||
|
||||
void icrdma_init_hw(struct irdma_sc_dev *dev)
|
||||
{
|
||||
int i;
|
||||
u8 __iomem *hw_addr;
|
||||
|
||||
for (i = 0; i < IRDMA_MAX_REGS; ++i) {
|
||||
hw_addr = dev->hw->hw_addr;
|
||||
|
||||
if (i == IRDMA_DB_ADDR_OFFSET)
|
||||
hw_addr = NULL;
|
||||
|
||||
dev->hw_regs[i] = (u32 __iomem *)(hw_addr + icrdma_regs[i]);
|
||||
}
|
||||
dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
|
||||
dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID;
|
||||
|
||||
for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
|
||||
dev->hw_shifts[i] = icrdma_shifts[i];
|
||||
|
||||
for (i = 0; i < IRDMA_MAX_MASKS; ++i)
|
||||
dev->hw_masks[i] = icrdma_masks[i];
|
||||
|
||||
dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
|
||||
dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
|
||||
dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
|
||||
dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
|
||||
dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
|
||||
dev->irq_ops = &icrdma_irq_ops;
|
||||
dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE;
|
||||
dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
|
||||
dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
|
||||
|
||||
dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
|
||||
dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |
|
||||
IRDMA_FEATURE_CQ_RESIZE;
|
||||
}
|
||||
71
drivers/infiniband/hw/irdma/icrdma_hw.h
Normal file
71
drivers/infiniband/hw/irdma/icrdma_hw.h
Normal file
@ -0,0 +1,71 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
|
||||
/* Copyright (c) 2017 - 2021 Intel Corporation */
|
||||
#ifndef ICRDMA_HW_H
|
||||
#define ICRDMA_HW_H
|
||||
|
||||
#include "irdma.h"
|
||||
|
||||
#define VFPE_CQPTAIL1 0x0000a000
|
||||
#define VFPE_CQPDB1 0x0000bc00
|
||||
#define VFPE_CCQPSTATUS1 0x0000b800
|
||||
#define VFPE_CCQPHIGH1 0x00009800
|
||||
#define VFPE_CCQPLOW1 0x0000ac00
|
||||
#define VFPE_CQARM1 0x0000b400
|
||||
#define VFPE_CQARM1 0x0000b400
|
||||
#define VFPE_CQACK1 0x0000b000
|
||||
#define VFPE_AEQALLOC1 0x0000a400
|
||||
#define VFPE_CQPERRCODES1 0x00009c00
|
||||
#define VFPE_WQEALLOC1 0x0000c000
|
||||
#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */
|
||||
|
||||
#define PFPE_CQPTAIL 0x00500880
|
||||
#define PFPE_CQPDB 0x00500800
|
||||
#define PFPE_CCQPSTATUS 0x0050a000
|
||||
#define PFPE_CCQPHIGH 0x0050a100
|
||||
#define PFPE_CCQPLOW 0x0050a080
|
||||
#define PFPE_CQARM 0x00502c00
|
||||
#define PFPE_CQACK 0x00502c80
|
||||
#define PFPE_AEQALLOC 0x00502d00
|
||||
#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */
|
||||
#define GLPCI_LBARCTRL 0x0009de74
|
||||
#define GLPE_CPUSTATUS0 0x0050ba5c
|
||||
#define GLPE_CPUSTATUS1 0x0050ba60
|
||||
#define GLPE_CPUSTATUS2 0x0050ba64
|
||||
#define PFINT_AEQCTL 0x0016cb00
|
||||
#define PFPE_CQPERRCODES 0x0050a200
|
||||
#define PFPE_WQEALLOC 0x00504400
|
||||
#define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */
|
||||
#define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */
|
||||
#define PFHMC_PDINV 0x00520300
|
||||
#define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */
|
||||
#define GLPE_CRITERR 0x00534000
|
||||
#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
|
||||
|
||||
#define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024)
|
||||
|
||||
#define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024)
|
||||
|
||||
/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
|
||||
#define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0
|
||||
#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
|
||||
#define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31
|
||||
#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
|
||||
#define ICRDMA_CQPSQ_STAG_PDID_S 46
|
||||
#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
|
||||
#define ICRDMA_CQPSQ_CQ_CEQID_S 22
|
||||
#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
|
||||
#define ICRDMA_CQPSQ_CQ_CQID_S 0
|
||||
#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
|
||||
#define ICRDMA_COMMIT_FPM_CQCNT_S 0
|
||||
#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
|
||||
|
||||
enum icrdma_device_caps_const {
|
||||
ICRDMA_MAX_STATS_COUNT = 128,
|
||||
|
||||
ICRDMA_MAX_IRD_SIZE = 127,
|
||||
ICRDMA_MAX_ORD_SIZE = 255,
|
||||
|
||||
};
|
||||
|
||||
void icrdma_init_hw(struct irdma_sc_dev *dev);
|
||||
#endif /* ICRDMA_HW_H*/
|
||||
Loading…
Reference in New Issue
Block a user