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clk: stm32mp1: add MCO clocks

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Two micro-controller clock output (MCO) pins are available:
MCO1 and MCO2.
For each output, it is possible to select a clock source.
The selected clock can be divided thanks to configurable
prescaler.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Gabriel Fernandez 2018-03-08 17:54:04 +01:00 committed by Michael Turquette
parent 2c87c9d331
commit 44cd455a8e
1 changed files with 20 additions and 0 deletions
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20
drivers/clk/clk-stm32mp1.c
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@ -252,6 +252,14 @@ static const char * const rtc_src[] = {
"off", "ck_lse", "ck_lsi", "ck_hse_rtc"
};
static const char * const mco1_src[] = {
"ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
};
static const char * const mco2_src[] = {
"ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
};
static const struct clk_div_table axi_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
@ -1960,6 +1968,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_MUX(RCC_BDCR, 16, 2, 0),
_NO_DIV),
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_NO_REPARENT,
_GATE(RCC_MCO1CFGR, 12, 0),
_MUX(RCC_MCO1CFGR, 0, 3, 0),
_DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_NO_REPARENT,
_GATE(RCC_MCO2CFGR, 12, 0),
_MUX(RCC_MCO2CFGR, 0, 3, 0),
_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
};
struct stm32_clock_match_data {