net: ipa: define some IPA endpoint register fields
Define the fields for the ENDP_INIT_CTRL, ENDP_INIT_CFG, ENDP_INIT_NAT, ENDP_INIT_HDR, and ENDP_INIT_HDR_EXT IPA registers for all supported IPA versions. Create enumerated types to identify fields for these IPA registers. Use IPA_REG_STRIDE_FIELDS() to specify the field mask values defined for these registers, for each supported version of IPA. Move ipa_header_size_encoded() and ipa_metadata_offset_encoded() out of "ipa_reg.h" and into "ipa_endpoint.c". Change them so they take an additional ipa_reg structure argument, and use ipa_reg_encode() to encode the parts of the header size and offset prior to writing to the register. Change their names to be verbs rather than nouns. Use ipa_reg_encode(), ipa_reg_bit, and ipa_reg_field_max() to manipulate values to be written to these registers, remove the definition of the no-longer-used *_FMASK symbols. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder
Jakub Kicinski
parent
1c418c4a92
commit
4468a3448b
@ -310,6 +310,7 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
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{
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struct ipa *ipa = endpoint->ipa;
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const struct ipa_reg *reg;
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u32 field_id;
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u32 offset;
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bool state;
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u32 mask;
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@ -321,10 +322,12 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
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WARN_ON(ipa->version >= IPA_VERSION_4_0);
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reg = ipa_reg(ipa, ENDP_INIT_CTRL);
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mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;
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offset = ipa_reg_n_offset(reg, endpoint->endpoint_id);
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val = ioread32(ipa->reg_virt + offset);
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field_id = endpoint->toward_ipa ? ENDP_DELAY : ENDP_SUSPEND;
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mask = ipa_reg_bit(reg, field_id);
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state = !!(val & mask);
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/* Don't bother if it's already in the requested state */
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@ -516,10 +519,8 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
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u32 off;
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/* Checksum header offset is in 4-byte units */
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off = sizeof(struct rmnet_map_header);
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off /= sizeof(u32);
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val |= u32_encode_bits(off,
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CS_METADATA_HDR_OFFSET_FMASK);
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off = sizeof(struct rmnet_map_header) / sizeof(u32);
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val |= ipa_reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
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enabled = version < IPA_VERSION_4_5
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? IPA_CS_OFFLOAD_UL
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@ -532,7 +533,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
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} else {
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enabled = IPA_CS_OFFLOAD_NONE;
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}
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val |= u32_encode_bits(enabled, CS_OFFLOAD_EN_FMASK);
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val |= ipa_reg_encode(reg, CS_OFFLOAD_EN, enabled);
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/* CS_GEN_QMB_MASTER_SEL is 0 */
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iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
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@ -549,7 +550,7 @@ static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint)
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return;
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reg = ipa_reg(ipa, ENDP_INIT_NAT);
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val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK);
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val = ipa_reg_encode(reg, NAT_EN, IPA_NAT_BYPASS);
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iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
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}
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@ -575,6 +576,50 @@ ipa_qmap_header_size(enum ipa_version version, struct ipa_endpoint *endpoint)
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return header_size;
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}
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/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */
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static u32 ipa_header_size_encode(enum ipa_version version,
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const struct ipa_reg *reg, u32 header_size)
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{
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u32 field_max = ipa_reg_field_max(reg, HDR_LEN);
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u32 val;
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/* We know field_max can be used as a mask (2^n - 1) */
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val = ipa_reg_encode(reg, HDR_LEN, header_size & field_max);
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if (version < IPA_VERSION_4_5) {
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WARN_ON(header_size > field_max);
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return val;
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}
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/* IPA v4.5 adds a few more most-significant bits */
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header_size >>= hweight32(field_max);
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WARN_ON(header_size > ipa_reg_field_max(reg, HDR_LEN_MSB));
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val |= ipa_reg_encode(reg, HDR_LEN_MSB, header_size);
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return val;
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}
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/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */
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static u32 ipa_metadata_offset_encode(enum ipa_version version,
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const struct ipa_reg *reg, u32 offset)
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{
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u32 field_max = ipa_reg_field_max(reg, HDR_OFST_METADATA);
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u32 val;
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/* We know field_max can be used as a mask (2^n - 1) */
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val = ipa_reg_encode(reg, HDR_OFST_METADATA, offset);
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if (version < IPA_VERSION_4_5) {
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WARN_ON(offset > field_max);
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return val;
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}
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/* IPA v4.5 adds a few more most-significant bits */
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offset >>= hweight32(field_max);
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WARN_ON(offset > ipa_reg_field_max(reg, HDR_OFST_METADATA_MSB));
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val |= ipa_reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
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return val;
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}
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/**
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* ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register
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* @endpoint: Endpoint pointer
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@ -609,7 +654,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
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size_t header_size;
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header_size = ipa_qmap_header_size(version, endpoint);
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val = ipa_header_size_encoded(version, header_size);
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val = ipa_header_size_encode(version, reg, header_size);
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/* Define how to fill fields in a received QMAP header */
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if (!endpoint->toward_ipa) {
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@ -617,19 +662,19 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
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/* Where IPA will write the metadata value */
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off = offsetof(struct rmnet_map_header, mux_id);
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val |= ipa_metadata_offset_encoded(version, off);
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val |= ipa_metadata_offset_encode(version, reg, off);
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/* Where IPA will write the length */
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off = offsetof(struct rmnet_map_header, pkt_len);
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/* Upper bits are stored in HDR_EXT with IPA v4.5 */
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if (version >= IPA_VERSION_4_5)
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off &= field_mask(HDR_OFST_PKT_SIZE_FMASK);
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off &= ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);
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val |= HDR_OFST_PKT_SIZE_VALID_FMASK;
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val |= u32_encode_bits(off, HDR_OFST_PKT_SIZE_FMASK);
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val |= ipa_reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);
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val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE, off);
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}
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/* For QMAP TX, metadata offset is 0 (modem assumes this) */
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val |= HDR_OFST_METADATA_VALID_FMASK;
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val |= ipa_reg_bit(reg, HDR_OFST_METADATA_VALID);
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/* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */
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/* HDR_A5_MUX is 0 */
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@ -651,7 +696,7 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
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reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT);
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if (endpoint->config.qmap) {
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/* We have a header, so we must specify its endianness */
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val |= HDR_ENDIANNESS_FMASK; /* big endian */
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val |= ipa_reg_bit(reg, HDR_ENDIANNESS); /* big endian */
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/* A QMAP header contains a 6 bit pad field at offset 0.
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* The RMNet driver assumes this field is meaningful in
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@ -661,16 +706,16 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
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* (although 0) should be ignored.
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*/
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if (!endpoint->toward_ipa) {
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val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;
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val |= ipa_reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);
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/* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
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val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;
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val |= ipa_reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);
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/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
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}
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}
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/* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
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if (!endpoint->toward_ipa)
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val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);
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val |= ipa_reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
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/* IPA v4.5 adds some most-significant bits to a few fields,
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* two of which are defined in the HDR (not HDR_EXT) register.
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@ -678,12 +723,13 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
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if (ipa->version >= IPA_VERSION_4_5) {
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/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
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if (endpoint->config.qmap && !endpoint->toward_ipa) {
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u32 mask = ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);
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u32 off; /* Field offset within header */
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off = offsetof(struct rmnet_map_header, pkt_len);
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off >>= hweight32(HDR_OFST_PKT_SIZE_FMASK);
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val |= u32_encode_bits(off,
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HDR_OFST_PKT_SIZE_MSB_FMASK);
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/* Low bits are in the ENDP_INIT_HDR register */
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off >>= hweight32(mask);
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val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
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/* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */
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}
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}
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@ -371,16 +371,18 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id {
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};
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/* ENDP_INIT_CTRL register */
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/* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */
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#define ENDP_SUSPEND_FMASK GENMASK(0, 0)
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/* Valid only for TX (IPA consumer) endpoints */
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#define ENDP_DELAY_FMASK GENMASK(1, 1)
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enum ipa_reg_endp_init_ctrl_field_id {
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ENDP_SUSPEND, /* Not v4.0+ */
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ENDP_DELAY, /* Not v4.2+ */
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};
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/* ENDP_INIT_CFG register */
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#define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0)
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#define CS_OFFLOAD_EN_FMASK GENMASK(2, 1)
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#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
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#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
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enum ipa_reg_endp_init_cfg_field_id {
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FRAG_OFFLOAD_EN,
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CS_OFFLOAD_EN,
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CS_METADATA_HDR_OFFSET,
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CS_GEN_QMB_MASTER_SEL,
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};
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/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
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enum ipa_cs_offload_en {
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@ -391,7 +393,9 @@ enum ipa_cs_offload_en {
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};
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/* ENDP_INIT_NAT register */
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#define NAT_EN_FMASK GENMASK(1, 0)
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enum ipa_reg_endp_init_nat_field_id {
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NAT_EN,
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};
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/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */
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enum ipa_nat_en {
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@ -401,72 +405,32 @@ enum ipa_nat_en {
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};
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/* ENDP_INIT_HDR register */
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#define HDR_LEN_FMASK GENMASK(5, 0)
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#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
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#define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
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#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)
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#define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19)
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#define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20)
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/* The next field is not present for IPA v4.9+ */
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#define HDR_A5_MUX_FMASK GENMASK(26, 26)
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#define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27)
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/* The next field is not present for IPA v4.5+ */
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#define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28)
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/* The next two fields are present for IPA v4.5+ */
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#define HDR_LEN_MSB_FMASK GENMASK(29, 28)
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#define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30)
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/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */
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static inline u32 ipa_header_size_encoded(enum ipa_version version,
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u32 header_size)
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{
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u32 size = header_size & field_mask(HDR_LEN_FMASK);
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u32 val;
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val = u32_encode_bits(size, HDR_LEN_FMASK);
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if (version < IPA_VERSION_4_5) {
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WARN_ON(header_size != size);
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return val;
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}
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/* IPA v4.5 adds a few more most-significant bits */
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size = header_size >> hweight32(HDR_LEN_FMASK);
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val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK);
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return val;
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}
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/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */
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static inline u32 ipa_metadata_offset_encoded(enum ipa_version version,
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u32 offset)
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{
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u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK);
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u32 val;
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val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK);
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if (version < IPA_VERSION_4_5) {
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WARN_ON(offset != off);
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return val;
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}
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/* IPA v4.5 adds a few more most-significant bits */
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off = offset >> hweight32(HDR_OFST_METADATA_FMASK);
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val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK);
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return val;
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}
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enum ipa_reg_endp_init_hdr_field_id {
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HDR_LEN,
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HDR_OFST_METADATA_VALID,
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HDR_OFST_METADATA,
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HDR_ADDITIONAL_CONST_LEN,
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HDR_OFST_PKT_SIZE_VALID,
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HDR_OFST_PKT_SIZE,
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HDR_A5_MUX, /* Not v4.9+ */
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HDR_LEN_INC_DEAGG_HDR,
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HDR_METADATA_REG_VALID, /* Not v4.5+ */
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HDR_LEN_MSB, /* v4.5+ */
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HDR_OFST_METADATA_MSB, /* v4.5+ */
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};
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/* ENDP_INIT_HDR_EXT register */
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#define HDR_ENDIANNESS_FMASK GENMASK(0, 0)
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#define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1)
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#define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2)
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#define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3)
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#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4)
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#define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10)
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/* The next three fields are present for IPA v4.5+ */
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#define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16)
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#define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18)
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#define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20)
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enum ipa_reg_endp_init_hdr_ext_field_id {
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HDR_ENDIANNESS,
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HDR_TOTAL_LEN_OR_PAD_VALID,
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HDR_TOTAL_LEN_OR_PAD,
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HDR_PAYLOAD_LEN_INC_PADDING,
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HDR_TOTAL_LEN_OR_PAD_OFFSET,
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HDR_PAD_TO_ALIGNMENT,
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HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */
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HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */
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HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */
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};
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/* ENDP_INIT_MODE register */
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#define MODE_FMASK GENMASK(2, 0)
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@ -238,15 +238,58 @@ static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
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IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
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0x0000050c, 0x0020);
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IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
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static const u32 ipa_reg_endp_init_ctrl_fmask[] = {
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[ENDP_SUSPEND] = BIT(0),
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[ENDP_DELAY] = BIT(1),
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/* Bits 2-31 reserved */
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};
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IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
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IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
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IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
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static const u32 ipa_reg_endp_init_cfg_fmask[] = {
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[FRAG_OFFLOAD_EN] = BIT(0),
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[CS_OFFLOAD_EN] = GENMASK(2, 1),
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[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
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/* Bit 7 reserved */
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[CS_GEN_QMB_MASTER_SEL] = BIT(8),
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/* Bits 9-31 reserved */
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};
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IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
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IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
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IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
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static const u32 ipa_reg_endp_init_nat_fmask[] = {
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[NAT_EN] = GENMASK(1, 0),
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/* Bits 2-31 reserved */
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};
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IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
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static const u32 ipa_reg_endp_init_hdr_fmask[] = {
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[HDR_LEN] = GENMASK(5, 0),
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[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
[HDR_A5_MUX] = BIT(26),
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_METADATA_REG_VALID] = BIT(28),
|
||||
/* Bits 29-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
@ -217,15 +217,58 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
|
||||
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
|
||||
0x00000504, 0x0020);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_ctrl_fmask[] = {
|
||||
[ENDP_SUSPEND] = BIT(0),
|
||||
[ENDP_DELAY] = BIT(1),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
|
||||
[FRAG_OFFLOAD_EN] = BIT(0),
|
||||
[CS_OFFLOAD_EN] = GENMASK(2, 1),
|
||||
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
|
||||
/* Bit 7 reserved */
|
||||
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
|
||||
/* Bits 9-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_nat_fmask[] = {
|
||||
[NAT_EN] = GENMASK(1, 0),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
|
||||
[HDR_LEN] = GENMASK(5, 0),
|
||||
[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
[HDR_A5_MUX] = BIT(26),
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_METADATA_REG_VALID] = BIT(28),
|
||||
/* Bits 29-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
@ -274,13 +274,54 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
|
||||
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
|
||||
0x00000504, 0x0020);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
|
||||
[FRAG_OFFLOAD_EN] = BIT(0),
|
||||
[CS_OFFLOAD_EN] = GENMASK(2, 1),
|
||||
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
|
||||
/* Bit 7 reserved */
|
||||
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
|
||||
/* Bits 9-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_nat_fmask[] = {
|
||||
[NAT_EN] = GENMASK(1, 0),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
|
||||
[HDR_LEN] = GENMASK(5, 0),
|
||||
[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
/* Bit 26 reserved */
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_LEN_MSB] = GENMASK(29, 28),
|
||||
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-15 reserved */
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
|
||||
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
|
||||
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
|
||||
/* Bits 22-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
@ -248,13 +248,50 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
|
||||
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
|
||||
0x00000504, 0x0020);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
|
||||
[FRAG_OFFLOAD_EN] = BIT(0),
|
||||
[CS_OFFLOAD_EN] = GENMASK(2, 1),
|
||||
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
|
||||
/* Bit 7 reserved */
|
||||
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
|
||||
/* Bits 9-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_nat_fmask[] = {
|
||||
[NAT_EN] = GENMASK(1, 0),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
|
||||
[HDR_LEN] = GENMASK(5, 0),
|
||||
[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
[HDR_A5_MUX] = BIT(26),
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_METADATA_REG_VALID] = BIT(28),
|
||||
/* Bits 29-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
@ -294,13 +294,54 @@ static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
|
||||
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
|
||||
0x00000508, 0x0020);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
|
||||
[FRAG_OFFLOAD_EN] = BIT(0),
|
||||
[CS_OFFLOAD_EN] = GENMASK(2, 1),
|
||||
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
|
||||
/* Bit 7 reserved */
|
||||
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
|
||||
/* Bits 9-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_nat_fmask[] = {
|
||||
[NAT_EN] = GENMASK(1, 0),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
|
||||
[HDR_LEN] = GENMASK(5, 0),
|
||||
[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
[HDR_A5_MUX] = BIT(26),
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_LEN_MSB] = GENMASK(29, 28),
|
||||
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-15 reserved */
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
|
||||
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
|
||||
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
|
||||
/* Bits 22-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
@ -272,13 +272,53 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
|
||||
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
|
||||
0x00000504, 0x0020);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_cfg_fmask[] = {
|
||||
[FRAG_OFFLOAD_EN] = BIT(0),
|
||||
[CS_OFFLOAD_EN] = GENMASK(2, 1),
|
||||
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
|
||||
/* Bit 7 reserved */
|
||||
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
|
||||
/* Bits 9-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
static const u32 ipa_reg_endp_init_nat_fmask[] = {
|
||||
[NAT_EN] = GENMASK(1, 0),
|
||||
/* Bits 2-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_fmask[] = {
|
||||
[HDR_LEN] = GENMASK(5, 0),
|
||||
[HDR_OFST_METADATA_VALID] = BIT(6),
|
||||
[HDR_OFST_METADATA] = GENMASK(12, 7),
|
||||
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
|
||||
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
|
||||
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
|
||||
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
|
||||
[HDR_LEN_MSB] = GENMASK(29, 28),
|
||||
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
|
||||
|
||||
static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {
|
||||
[HDR_ENDIANNESS] = BIT(0),
|
||||
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
|
||||
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
|
||||
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
|
||||
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
|
||||
/* Bits 14-15 reserved */
|
||||
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
|
||||
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
|
||||
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
|
||||
/* Bits 22-31 reserved */
|
||||
};
|
||||
|
||||
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
|
||||
|
||||
IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
|
||||
0x00000818, 0x0070);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user