drm/amd/amdgpu: Define and implement a function that collects number of
waves that are in flight. [Why] Allow user to know how many compute units (CU) are in use at any given moment. [How] Read registers of SQ that give number of waves that are in flight of various queues. Use this information to determine number of CU's in use. Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-By: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ramesh Errabolu
Alex Deucher
parent
39ad082459
commit
43a4bc828c
@ -36,6 +36,7 @@
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#include "v9_structs.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "gfx_v9_0.h"
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enum hqd_dequeue_request_type {
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NO_ACTION = 0,
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@ -703,6 +704,179 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd,
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adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
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}
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static void lock_spi_csq_mutexes(struct amdgpu_device *adev)
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{
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mutex_lock(&adev->srbm_mutex);
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mutex_lock(&adev->grbm_idx_mutex);
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}
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static void unlock_spi_csq_mutexes(struct amdgpu_device *adev)
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{
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mutex_unlock(&adev->grbm_idx_mutex);
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mutex_unlock(&adev->srbm_mutex);
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}
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/**
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* @get_wave_count: Read device registers to get number of waves in flight for
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* a particular queue. The method also returns the VMID associated with the
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* queue.
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*
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* @adev: Handle of device whose registers are to be read
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* @queue_idx: Index of queue in the queue-map bit-field
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* @wave_cnt: Output parameter updated with number of waves in flight
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* @vmid: Output parameter updated with VMID of queue whose wave count
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* is being collected
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*/
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static void get_wave_count(struct amdgpu_device *adev, int queue_idx,
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int *wave_cnt, int *vmid)
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{
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int pipe_idx;
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int queue_slot;
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unsigned int reg_val;
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/*
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* Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID
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* parameters to read out waves in flight. Get VMID if there are
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* non-zero waves in flight.
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*/
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*vmid = 0xFF;
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*wave_cnt = 0;
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pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;
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queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;
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soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);
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reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
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queue_slot);
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*wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;
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if (*wave_cnt != 0)
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*vmid = (RREG32_SOC15(GC, 0, mmCP_HQD_VMID) &
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CP_HQD_VMID__VMID_MASK) >> CP_HQD_VMID__VMID__SHIFT;
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}
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/**
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* @kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each
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* shader engine and aggregates the number of waves that are in flight for the
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* process whose pasid is provided as a parameter. The process could have ZERO
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* or more queues running and submitting waves to compute units.
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*
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* @kgd: Handle of device from which to get number of waves in flight
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* @pasid: Identifies the process for which this query call is invoked
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* @wave_cnt: Output parameter updated with number of waves in flight that
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* belong to process with given pasid
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* @max_waves_per_cu: Output parameter updated with maximum number of waves
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* possible per Compute Unit
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*
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* @note: It's possible that the device has too many queues (oversubscription)
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* in which case a VMID could be remapped to a different PASID. This could lead
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* to an iaccurate wave count. Following is a high-level sequence:
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* Time T1: vmid = getVmid(); vmid is associated with Pasid P1
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* Time T2: passId = getPasId(vmid); vmid is associated with Pasid P2
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* In the sequence above wave count obtained from time T1 will be incorrectly
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* lost or added to total wave count.
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*
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* The registers that provide the waves in flight are:
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*
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* SPI_CSQ_WF_ACTIVE_STATUS - bit-map of queues per pipe. The bit is ON if a
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* queue is slotted, OFF if there is no queue. A process could have ZERO or
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* more queues slotted and submitting waves to be run on compute units. Even
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* when there is a queue it is possible there could be zero wave fronts, this
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* can happen when queue is waiting on top-of-pipe events - e.g. waitRegMem
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* command
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*
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* For each bit that is ON from above:
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*
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* Read (SPI_CSQ_WF_ACTIVE_COUNT_0 + queue_idx) register. It provides the
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* number of waves that are in flight for the queue at specified index. The
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* index ranges from 0 to 7.
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*
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* If non-zero waves are in flight, read CP_HQD_VMID register to obtain VMID
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* of the wave(s).
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*
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* Determine if VMID from above step maps to pasid provided as parameter. If
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* it matches agrregate the wave count. That the VMID will not match pasid is
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* a normal condition i.e. a device is expected to support multiple queues
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* from multiple proceses.
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*
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* Reading registers referenced above involves programming GRBM appropriately
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*/
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static void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,
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int *pasid_wave_cnt, int *max_waves_per_cu)
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{
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int qidx;
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int vmid;
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int se_idx;
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int sh_idx;
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int se_cnt;
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int sh_cnt;
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int wave_cnt;
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int queue_map;
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int pasid_tmp;
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int max_queue_cnt;
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int vmid_wave_cnt = 0;
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struct amdgpu_device *adev;
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DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
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adev = get_amdgpu_device(kgd);
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lock_spi_csq_mutexes(adev);
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soc15_grbm_select(adev, 1, 0, 0, 0);
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/*
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* Iterate through the shader engines and arrays of the device
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* to get number of waves in flight
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*/
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bitmap_complement(cp_queue_bitmap, adev->gfx.mec.queue_bitmap,
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KGD_MAX_QUEUES);
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max_queue_cnt = adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe;
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sh_cnt = adev->gfx.config.max_sh_per_se;
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se_cnt = adev->gfx.config.max_shader_engines;
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for (se_idx = 0; se_idx < se_cnt; se_idx++) {
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for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {
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gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
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queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,
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mmSPI_CSQ_WF_ACTIVE_STATUS));
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/*
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* Assumption: queue map encodes following schema: four
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* pipes per each micro-engine, with each pipe mapping
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* eight queues. This schema is true for GFX9 devices
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* and must be verified for newer device families
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*/
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for (qidx = 0; qidx < max_queue_cnt; qidx++) {
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/* Skip qeueus that are not associated with
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* compute functions
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*/
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if (!test_bit(qidx, cp_queue_bitmap))
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continue;
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if (!(queue_map & (1 << qidx)))
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continue;
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/* Get number of waves in flight and aggregate them */
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get_wave_count(adev, qidx, &wave_cnt, &vmid);
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if (wave_cnt != 0) {
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pasid_tmp =
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RREG32(SOC15_REG_OFFSET(OSSSYS, 0,
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mmIH_VMID_0_LUT) + vmid);
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if (pasid_tmp == pasid)
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vmid_wave_cnt += wave_cnt;
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}
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}
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}
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}
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gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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soc15_grbm_select(adev, 0, 0, 0, 0);
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unlock_spi_csq_mutexes(adev);
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/* Update the output parameters and return */
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*pasid_wave_cnt = vmid_wave_cnt;
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*max_waves_per_cu = adev->gfx.cu_info.simd_per_cu *
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adev->gfx.cu_info.max_waves_per_simd;
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}
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const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
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.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
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@ -723,4 +897,5 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
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.get_atc_vmid_pasid_mapping_info =
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kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
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.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
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.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
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};
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@ -212,6 +212,15 @@ struct tile_config {
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* IH ring entry. This function allows the KFD ISR to get the VMID
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* from the fault status register as early as possible.
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*
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* @get_cu_occupancy: Function pointer that returns to caller the number
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* of wave fronts that are in flight for all of the queues of a process
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* as identified by its pasid. It is important to note that the value
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* returned by this function is a snapshot of current moment and cannot
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* guarantee any minimum for the number of waves in-flight. This function
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* is defined for devices that belong to GFX9 and later GFX families. Care
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* must be taken in calling this function as it is not defined for devices
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* that belong to GFX8 and below GFX families.
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*
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* This structure contains function pointers to services that the kgd driver
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* provides to amdkfd driver.
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*
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@ -286,6 +295,9 @@ struct kfd2kgd_calls {
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void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
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uint32_t vmid, uint64_t page_table_base);
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uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
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void (*get_cu_occupancy)(struct kgd_dev *kgd, int pasid, int *wave_cnt,
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int *max_waves_per_cu);
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};
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#endif /* KGD_KFD_INTERFACE_H_INCLUDED */
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