forked from Minki/linux
drm/nouveau/dp: rewrite auxch transaction routines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
91a8f1ea4b
commit
4372013388
@ -29,6 +29,136 @@
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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/******************************************************************************
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* aux channel util functions
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*****************************************************************************/
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#define AUX_DBG(fmt, args...) do { \
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if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
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NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
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} \
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} while (0)
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#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
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static void
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auxch_fini(struct drm_device *dev, int ch)
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{
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nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
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}
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static int
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auxch_init(struct drm_device *dev, int ch)
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{
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const u32 unksel = 1; /* nfi which to use, or if it matters.. */
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const u32 ureq = unksel ? 0x00100000 : 0x00200000;
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const u32 urep = unksel ? 0x01000000 : 0x02000000;
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u32 ctrl, timeout;
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/* wait up to 1ms for any previous transaction to be done... */
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("begin idle timeout 0x%08x", ctrl);
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return -EBUSY;
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}
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} while (ctrl & 0x03010000);
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/* set some magic, and wait up to 1ms for it to appear */
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nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("magic wait 0x%08x\n", ctrl);
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auxch_fini(dev, ch);
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return -EBUSY;
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}
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} while ((ctrl & 0x03000000) != urep);
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return 0;
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}
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static int
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auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
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{
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u32 ctrl, stat, timeout, retries;
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u32 xbuf[4] = {};
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int ret, i;
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AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
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ret = auxch_init(dev, ch);
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if (ret)
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goto out;
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stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
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if (!(stat & 0x10000000)) {
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AUX_DBG("sink not detected\n");
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ret = -ENXIO;
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goto out;
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}
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if (!(type & 1)) {
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memcpy(xbuf, data, size);
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for (i = 0; i < 16; i += 4) {
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AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
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nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
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}
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}
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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ctrl &= ~0x0001f0ff;
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ctrl |= type << 12;
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ctrl |= size - 1;
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nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
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/* retry transaction a number of times on failure... */
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ret = -EREMOTEIO;
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for (retries = 0; retries < 32; retries++) {
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/* reset, and delay a while if this is a retry */
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
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if (retries)
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udelay(400);
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/* transaction request, wait up to 1ms for it to complete */
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("tx req timeout 0x%08x\n", ctrl);
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goto out;
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}
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} while (ctrl & 0x00010000);
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/* read status, and check if transaction completed ok */
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stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
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if (!(stat & 0x000f0f00)) {
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ret = 0;
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break;
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}
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AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
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}
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if (type & 1) {
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for (i = 0; i < 16; i += 4) {
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xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
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AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
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}
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memcpy(data, xbuf, size);
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}
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out:
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auxch_fini(dev, ch);
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return ret;
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}
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static int
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auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
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{
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@ -480,98 +610,7 @@ int
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nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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uint8_t *data, int data_nr)
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{
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struct drm_device *dev = auxch->dev;
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uint32_t tmp, ctrl, stat = 0, data32[4] = {};
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int ret = 0, i, index = auxch->rd;
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NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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if (!(tmp & 0x01000000)) {
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NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
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ret = -EIO;
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goto out;
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}
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for (i = 0; i < 3; i++) {
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tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
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if (tmp & NV50_AUXCH_STAT_STATE_READY)
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break;
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udelay(100);
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}
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if (i == 3) {
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ret = -EBUSY;
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goto out;
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}
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if (!(cmd & 1)) {
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memcpy(data32, data, data_nr);
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for (i = 0; i < 4; i++) {
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NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
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nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
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}
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}
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nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
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ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
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ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
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ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
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ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
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for (i = 0; i < 16; i++) {
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nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
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nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
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nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
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if (!nv_wait(dev, NV50_AUXCH_CTRL(index),
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0x00010000, 0x00000000)) {
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NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
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nv_rd32(dev, NV50_AUXCH_CTRL(index)));
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ret = -EBUSY;
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goto out;
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}
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udelay(400);
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stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
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if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
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NV50_AUXCH_STAT_REPLY_AUX_DEFER)
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break;
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}
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if (i == 16) {
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NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
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ret = -EREMOTEIO;
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goto out;
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}
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if (cmd & 1) {
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if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
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ret = -EREMOTEIO;
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goto out;
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}
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for (i = 0; i < 4; i++) {
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data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
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NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
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}
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memcpy(data, data32, data_nr);
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}
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out:
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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if (tmp & 0x01000000) {
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NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
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ret = -EIO;
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}
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udelay(400);
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return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
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return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
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}
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static int
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@ -602,19 +641,6 @@ nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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if (ret < 0)
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return ret;
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switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
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case NV50_AUXCH_STAT_REPLY_I2C_ACK:
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break;
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case NV50_AUXCH_STAT_REPLY_I2C_NACK:
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return -EREMOTEIO;
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case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
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udelay(100);
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continue;
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default:
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NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret);
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return -EREMOTEIO;
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}
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ptr += cnt;
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remaining -= cnt;
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}
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@ -1570,6 +1570,7 @@ enum {
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NOUVEAU_REG_DEBUG_RMVIO = 0x80,
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NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
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NOUVEAU_REG_DEBUG_EVO = 0x200,
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NOUVEAU_REG_DEBUG_AUXCH = 0x400
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};
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#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
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