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dt-bindings: mailbox: convert stm32-ipcc to json-schema

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Convert the STM32 IPCC bindings to DT schema format using
json-schema

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Arnaud Pouliquen 2019-11-21 10:51:02 +01:00 committed by Rob Herring
parent b88091f5d8
commit 4360bf7244
2 changed files with 84 additions and 47 deletions
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84
Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: STMicroelectronics STM32 IPC controller bindings
description:
The IPCC block provides a non blocking signaling mechanism to post and
retrieve messages in an atomic way between two processors.
It provides the signaling for N bidirectionnal channels. The number of
channels (N) can be read from a dedicated register.
maintainers:
- Fabien Dessenne <fabien.dessenne@st.com>
- Arnaud Pouliquen <arnaud.pouliquen@st.com>
properties:
compatible:
const: st,stm32mp1-ipcc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
items:
- description: rx channel occupied
- description: tx channel free
- description: wakeup source
minItems: 2
maxItems: 3
interrupt-names:
items:
- const: rx
- const: tx
- const: wakeup
minItems: 2
maxItems: 3
wakeup-source: true
"#mbox-cells":
const: 1
st,proc-id:
description: Processor id using the mailbox (0 or 1)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
required:
- compatible
- reg
- st,proc-id
- clocks
- interrupt-names
- "#mbox-cells"
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
<&aiec 62 1>;
interrupt-names = "rx", "tx", "wakeup";
clocks = <&rcc_clk IPCC>;
wakeup-source;
};
...

47
Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
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* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
The IPCC block provides a non blocking signaling mechanism to post and
retrieve messages in an atomic way between two processors.
It provides the signaling for N bidirectionnal channels. The number of channels
(N) can be read from a dedicated register.
Required properties:
- compatible: Must be "st,stm32mp1-ipcc"
- reg: Register address range (base address and length)
- st,proc-id: Processor id using the mailbox (0 or 1)
- clocks: Input clock
- interrupt-names: List of names for the interrupts described by the interrupt
property. Must contain the following entries:
- "rx"
- "tx"
- "wakeup"
- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
free" and "system wakeup".
- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
The data contained in the mbox specifier of the "mboxes"
property in the client node is the mailbox channel index.
Optional properties:
- wakeup-source: Flag to indicate whether this device can wake up the system
Example:
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
<&aiec 62 1>;
interrupt-names = "rx", "tx", "wakeup";
clocks = <&rcc_clk IPCC>;
wakeup-source;
}
Client:
mbox_test {
...
mboxes = <&ipcc 0>, <&ipcc 1>;
};