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Merge branch 'mlxsw-unified-bridge-conversion-part-1'

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Ido Schimmel says:

====================
mlxsw: Unified bridge conversion - part 1/6

This set starts converting mlxsw to the unified bridge model and mainly
adds new device registers and extends existing ones that will be used in
follow-up patchsets.

High-level summary
==================

The unified bridge model is a new way of managing low-level device
objects such as filtering identifiers (FIDs). The conversion moves a lot
of logic out of the device's firmware towards the driver, but its main
selling point is that it allows to overcome various scalability issues
related to the amount of entries that need to be programmed to the
device.

The only (intended) user visible changes of the conversion are
improvement in resource utilization and ability to support more router
interfaces (RIFs) in Spectrum-{2,3}.

Details
=======

Commit 50853808ff ("Merge branch
'mlxsw-Prepare-for-VLAN-aware-bridge-w-VxLAN'") converted mlxsw to
emulate 802.1Q FIDs (represent VLANs in a VLAN-aware bridge) using
802.1D FIDs (represent VLAN-unaware bridges). This was necessary because
at that time VNI could not be assigned to 802.1Q FIDs, which effectively
meant that mlxsw could not support VXLAN with VLAN-aware bridges.

The downside of this approach is that multiple {Port,VID}->FID entries
are required in order to classify incoming traffic to a FID, as opposed
to a single VID->FID entry that can be used with actual 802.1Q FIDs.

For example, if 10 ports are members in the same VLAN-aware bridge and
the same 100 VLANs are configured on each port, then only 100 VID->FID
entries are required with 802.1Q FIDs, whereas 1000 {Port,VID}->FID
entries are required with emulated 802.1Q FIDs.

The above limitation is the result of various assumptions that were made
in the design of the API that was exposed to software. In the unified
bridge model the API is much more "raw" and therefore avoids these
assumptions, allowing software to configure the device in a more
efficient manner.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2022-06-20 10:03:34 +01:00
parent a56b158a50 b382092265
commit 4336487e30
4 changed files with 335 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/mellanox/mlxsw/port.h
View File

@@ -15,8 +15,6 @@
#define MLXSW_PORT_SWID_TYPE_IB 1
#define MLXSW_PORT_SWID_TYPE_ETH 2
#define MLXSW_PORT_MID 0xd000
#define MLXSW_PORT_MAX_IB_PHY_PORTS 36
#define MLXSW_PORT_MAX_IB_PORTS (MLXSW_PORT_MAX_IB_PHY_PORTS + 1)

353
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@@ -322,6 +322,18 @@ MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_set_vid
* Set VID.
* 0 - Do not update VID.
* 1 - Set VID.
* For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_fid_vid
* Filtering ID or VLAN ID
* For SwitchX and SwitchX-2:
@@ -335,6 +347,15 @@ MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_vid
* New VID when set_vid=1.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and when set_vid=0.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_system_port
* Unique port identifier for the final destination of the packet.
* Access: RW
@@ -379,6 +400,18 @@ static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_set_vid
* Set VID.
* 0 - Do not update VID.
* 1 - Set VID.
* For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_fid_vid
* Filtering ID or VLAN ID
* For SwitchX and SwitchX-2:
@@ -393,8 +426,10 @@ MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_lag_vid
* Indicates VID in case of vFIDs. Reserved for FIDs.
* New vlan ID.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and set_vid=0.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
@@ -997,7 +1032,7 @@ static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
* to packet types used for flooding.
*/
#define MLXSW_REG_SFGC_ID 0x2011
#define MLXSW_REG_SFGC_LEN 0x10
#define MLXSW_REG_SFGC_LEN 0x14
MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
@@ -1054,12 +1089,6 @@ MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
*/
MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
/* reg_sfgc_mid
* The multicast ID for the swid. Not supported for Spectrum
* Access: RW
*/
MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
/* reg_sfgc_counter_set_type
* Counter Set Type for flow counters.
* Access: RW
@@ -1072,6 +1101,14 @@ MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
*/
MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
/* reg_sfgc_mid_base
* MID Base.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
static inline void
mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
enum mlxsw_reg_sfgc_bridge_type bridge_type,
@@ -1083,7 +1120,6 @@ mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
mlxsw_reg_sfgc_table_type_set(payload, table_type);
mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
}
/* SFDF - Switch Filtering DB Flush
@@ -1516,7 +1552,7 @@ static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
* virtualized ports.
*/
#define MLXSW_REG_SVFA_ID 0x201C
#define MLXSW_REG_SVFA_LEN 0x10
#define MLXSW_REG_SVFA_LEN 0x18
MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
@@ -1537,6 +1573,7 @@ MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
enum mlxsw_reg_svfa_mt {
MLXSW_REG_SVFA_MT_VID_TO_FID,
MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
MLXSW_REG_SVFA_MT_VNI_TO_FID,
};
/* reg_svfa_mapping_table
@@ -1586,20 +1623,73 @@ MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
*/
MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
static inline void mlxsw_reg_svfa_pack(char *payload, u16 local_port,
enum mlxsw_reg_svfa_mt mt, bool valid,
u16 fid, u16 vid)
/* reg_svfa_vni
* Virtual Network Identifier.
* Access: Index
*
* Note: Reserved when mapping_table is not 2 (VNI mapping table).
*/
MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
/* reg_svfa_irif_v
* Ingress RIF valid.
* 0 - Ingress RIF is not valid, no ingress RIF assigned.
* 1 - Ingress RIF valid.
* Must not be set for a non enabled RIF.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
/* reg_svfa_irif
* Ingress RIF (Router Interface).
* Range is 0..cap_max_router_interfaces-1.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and when irif_v=0.
*/
MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
static inline void __mlxsw_reg_svfa_pack(char *payload,
enum mlxsw_reg_svfa_mt mt, bool valid,
u16 fid)
{
MLXSW_REG_ZERO(svfa, payload);
local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
mlxsw_reg_svfa_swid_set(payload, 0);
mlxsw_reg_svfa_local_port_set(payload, local_port);
mlxsw_reg_svfa_mapping_table_set(payload, mt);
mlxsw_reg_svfa_v_set(payload, valid);
mlxsw_reg_svfa_fid_set(payload, fid);
}
static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,
bool valid, u16 fid, u16 vid)
{
enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
__mlxsw_reg_svfa_pack(payload, mt, valid, fid);
mlxsw_reg_svfa_local_port_set(payload, local_port);
mlxsw_reg_svfa_vid_set(payload, vid);
}
static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,
u16 vid)
{
enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
__mlxsw_reg_svfa_pack(payload, mt, valid, fid);
mlxsw_reg_svfa_vid_set(payload, vid);
}
static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,
u32 vni)
{
enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;
__mlxsw_reg_svfa_pack(payload, mt, valid, fid);
mlxsw_reg_svfa_vni_set(payload, vni);
}
/* SPVTR - Switch Port VLAN Stacking Register
* ------------------------------------------
* The Switch Port VLAN Stacking register configures the VLAN mode of the port
@@ -1741,7 +1831,7 @@ static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
* Creates and configures FIDs.
*/
#define MLXSW_REG_SFMR_ID 0x201F
#define MLXSW_REG_SFMR_LEN 0x18
#define MLXSW_REG_SFMR_LEN 0x30
MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
@@ -1764,6 +1854,28 @@ MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
*/
MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
/* reg_sfmr_flood_rsp
* Router sub-port flooding table.
* 0 - Regular flooding table.
* 1 - Router sub-port flooding table. For this FID the flooding is per
* router-sub-port local_port. Must not be set for a FID which is not a
* router-sub-port and must be set prior to enabling the relevant RIF.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
/* reg_sfmr_flood_bridge_type
* Flood bridge type (see SFGC.bridge_type).
* 0 - type_0.
* 1 - type_1.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and when flood_rsp=1.
*/
MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
/* reg_sfmr_fid_offset
* FID offset.
* Used to point into the flooding table selected by SFGC register if
@@ -1800,12 +1912,52 @@ MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
/* reg_sfmr_vni
* Virtual Network Identifier.
* When legacy bridge model is used, a given VNI can only be assigned to one
* FID. When unified bridge model is used, it configures only the FID->VNI,
* the VNI->FID is done by SVFA.
* Access: RW
*
* Note: A given VNI can only be assigned to one FID.
*/
MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
/* reg_sfmr_irif_v
* Ingress RIF valid.
* 0 - Ingress RIF is not valid, no ingress RIF assigned.
* 1 - Ingress RIF valid.
* Must not be set for a non valid RIF.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
/* reg_sfmr_irif
* Ingress RIF (Router Interface).
* Range is 0..cap_max_router_interfaces-1.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and when irif_v=0.
*/
MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
/* reg_sfmr_smpe_valid
* SMPE is valid.
* Access: RW
*
* Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
* Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
/* reg_sfmr_smpe
* Switch multicast port to egress VID.
* Range is 0..cap_max_rmpe-1
* Access: RW
*
* Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
* Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
static inline void mlxsw_reg_sfmr_pack(char *payload,
enum mlxsw_reg_sfmr_op op, u16 fid,
u16 fid_offset)
@@ -2013,6 +2165,45 @@ static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
}
/* SMPE - Switch Multicast Port to Egress VID
* ------------------------------------------
* The switch multicast port to egress VID maps
* {egress_port, SMPE index} -> {VID}.
*/
#define MLXSW_REG_SMPE_ID 0x202B
#define MLXSW_REG_SMPE_LEN 0x0C
MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN);
/* reg_smpe_local_port
* Local port number.
* CPU port is not supported.
* Access: Index
*/
MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
/* reg_smpe_smpe_index
* Switch multicast port to egress VID.
* Range is 0..cap_max_rmpe-1.
* Access: Index
*/
MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
/* reg_smpe_evid
* Egress VID.
* Access: RW
*/
MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);
static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port,
u16 smpe_index, u16 evid)
{
MLXSW_REG_ZERO(smpe, payload);
mlxsw_reg_smpe_local_port_set(payload, local_port);
mlxsw_reg_smpe_smpe_index_set(payload, smpe_index);
mlxsw_reg_smpe_evid_set(payload, evid);
}
/* SFTR-V2 - Switch Flooding Table Version 2 Register
* --------------------------------------------------
* The switch flooding table is used for flooding packet replication. The table
@@ -2107,6 +2298,23 @@ MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
*/
MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
/* reg_smid2_smpe_valid
* SMPE is valid.
* When not valid, the egress VID will not be modified by the SMPE table.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
/* reg_smid2_smpe
* Switch multicast port to egress VID.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
/* reg_smid2_port
* Local port memebership (1 bit per port).
* Access: RW
@@ -2120,13 +2328,15 @@ MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
bool set)
bool set, bool smpe_valid, u16 smpe)
{
MLXSW_REG_ZERO(smid2, payload);
mlxsw_reg_smid2_swid_set(payload, 0);
mlxsw_reg_smid2_mid_set(payload, mid);
mlxsw_reg_smid2_port_set(payload, port, set);
mlxsw_reg_smid2_port_mask_set(payload, port, 1);
mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid);
mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0);
}
/* CWTP - Congetion WRED ECN TClass Profile
@@ -6701,17 +6911,28 @@ MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
/* VLAN Interface */
/* reg_ritr_vlan_if_vid
/* reg_ritr_vlan_if_vlan_id
* VLAN ID.
* Access: RW
*/
MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12);
/* reg_ritr_vlan_if_efid
* Egress FID.
* Used to connect the RIF to a bridge.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and on Spectrum-1.
*/
MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);
/* FID Interface */
/* reg_ritr_fid_if_fid
* Filtering ID. Used to connect a bridge to the router. Only FIDs from
* the vFID range are supported.
* Filtering ID. Used to connect a bridge to the router.
* When legacy bridge model is used, only FIDs from the vFID range are
* supported. When unified bridge model is used, this is the egress FID for
* router to bridge.
* Access: RW
*/
MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
@@ -6723,7 +6944,7 @@ static inline void mlxsw_reg_ritr_fid_set(char *payload,
if (rif_type == MLXSW_REG_RITR_FID_IF)
mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
else
mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, fid);
}
/* Sub-port Interface */
@@ -6742,6 +6963,16 @@ MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
*/
MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
/* reg_ritr_sp_if_efid
* Egress filtering ID.
* Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or
* the VID.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);
/* reg_ritr_sp_if_vid
* VLAN ID.
* Access: RW
@@ -6917,6 +7148,20 @@ static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
}
static inline void
mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id,
u16 mtu, const char *mac, u8 mac_profile_id,
u16 vlan_id, u16 efid)
{
enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF;
mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu);
mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id);
mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id);
mlxsw_reg_ritr_vlan_if_efid_set(payload, efid);
}
static inline void
mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
@@ -8924,6 +9169,64 @@ mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
}
/* REIV - Router Egress Interface to VID Register
* ----------------------------------------------
* The REIV register maps {eRIF, egress_port} -> VID.
* This mapping is done at the egress, after the ACLs.
* This mapping always takes effect after router, regardless of cast
* (for unicast/multicast/port-base multicast), regardless of eRIF type and
* regardless of bridge decisions (e.g. SFD for unicast or SMPE).
* Reserved when the RIF is a loopback RIF.
*
* Note: Reserved when legacy bridge model is used.
*/
#define MLXSW_REG_REIV_ID 0x8034
#define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */
#define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */
#define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */
#define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \
MLXSW_REG_REIV_REC_LEN * \
MLXSW_REG_REIV_REC_MAX_COUNT)
MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN);
/* reg_reiv_port_page
* Port page - elport_record[0] is 256*port_page.
* Access: Index
*/
MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4);
/* reg_reiv_erif
* Egress RIF.
* Range is 0..cap_max_router_interfaces-1.
* Access: Index
*/
MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16);
/* reg_reiv_rec_update
* Update enable (when write):
* 0 - Do not update the entry.
* 1 - Update the entry.
* Access: OP
*/
MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1,
MLXSW_REG_REIV_REC_LEN, 0x00, false);
/* reg_reiv_rec_evid
* Egress VID.
* Range is 0..4095.
* Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12,
MLXSW_REG_REIV_REC_LEN, 0x00, false);
static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif)
{
MLXSW_REG_ZERO(reiv, payload);
mlxsw_reg_reiv_port_page_set(payload, port_page);
mlxsw_reg_reiv_erif_set(payload, erif);
}
/* MFCR - Management Fan Control Register
* --------------------------------------
* This register controls the settings of the Fan Speed PWM mechanism.
@@ -12357,6 +12660,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(spvmlr),
MLXSW_REG(spvc),
MLXSW_REG(spevet),
MLXSW_REG(smpe),
MLXSW_REG(sftr2),
MLXSW_REG(smid2),
MLXSW_REG(cwtp),
@@ -12430,6 +12734,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(rigr2),
MLXSW_REG(recr2),
MLXSW_REG(rmft2),
MLXSW_REG(reiv),
MLXSW_REG(mfcr),
MLXSW_REG(mfsc),
MLXSW_REG(mfsm),

4
drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c
View File

@@ -441,10 +441,10 @@ static int mlxsw_sp_fid_vni_op(struct mlxsw_sp *mlxsw_sp, u16 fid_index,
static int __mlxsw_sp_fid_port_vid_map(struct mlxsw_sp *mlxsw_sp, u16 fid_index,
u16 local_port, u16 vid, bool valid)
{
enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
char svfa_pl[MLXSW_REG_SVFA_LEN];
mlxsw_reg_svfa_pack(svfa_pl, local_port, mt, valid, fid_index, vid);
mlxsw_reg_svfa_port_vid_pack(svfa_pl, local_port, valid, fid_index,
vid);
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
}

7
drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c
View File

@@ -887,7 +887,7 @@ static int mlxsw_sp_smid_router_port_set(struct mlxsw_sp *mlxsw_sp,
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx,
mlxsw_sp_router_port(mlxsw_sp), add);
mlxsw_sp_router_port(mlxsw_sp), add, false, 0);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);
kfree(smid2_pl);
return err;
@@ -1584,7 +1584,7 @@ static int mlxsw_sp_port_smid_full_entry(struct mlxsw_sp *mlxsw_sp, u16 mid_idx,
if (!smid2_pl)
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, 0, false);
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, 0, false, false, 0);
for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) {
if (mlxsw_sp->ports[i])
mlxsw_reg_smid2_port_mask_set(smid2_pl, i, 1);
@@ -1615,7 +1615,8 @@ static int mlxsw_sp_port_smid_set(struct mlxsw_sp_port *mlxsw_sp_port,
if (!smid2_pl)
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, mlxsw_sp_port->local_port, add);
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, mlxsw_sp_port->local_port, add,
false, 0);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);
kfree(smid2_pl);
return err;