Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.8. Also includes is a
minor SSB cleanup as SSB code traditionally is merged through the MIPS
tree:
ATH25:
- MIPS: Add default configuration for ath25
Boot:
- For zboot, copy appended dtb to the end of the kernel
- store the appended dtb address in a variable
BPF:
- Fix off by one error in offset allocation
Cobalt code:
- Fix typos
Core code:
- debugfs_create_file returns NULL on error, so don't use IS_ERR for
testing for errors.
- Fix double locking issue in RM7000 S-cache code. This would only
affect RM7000 ARC systems on reboot.
- Fix page table corruption on THP permission changes.
- Use compat_sys_keyctl for 32 bit userspace on 64 bit kernels.
David says, there are no compatibility issues raised by this fix.
- Move some signal code around.
- Rewrite r4k count/compare clockevent device registration such that
min_delta_ticks/max_delta_ticks files are guaranteed to be
initialized.
- Only register r4k count/compare as clockevent device if we can
assume the clock to be constant.
- Fix MSA asm warnings in control reg accessors
- uasm and tlbex fixes and tweaking.
- Print segment physical address when EU=1.
- Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO.
- CP: Allow booting by VP other than VP 0
- Cache handling fixes and optimizations for r4k class caches
- Add hotplug support for R6 processors
- Cleanup hotplug bits in kconfig
- traps: return correct si code for accessing nonmapped addresses
- Remove cpu_has_safe_index_cacheops
Lantiq:
- Register IRQ handler for virtual IRQ number
- Fix EIU interrupt loading code
- Use the real EXIN count
- Fix build error.
Loongson 3:
- Increase HPET_MIN_PROG_DELTA and decrease HPET_MIN_CYCLES
Octeon:
- Delete built-in DTB pruning code for D-Link DSR-1000N.
- Clean up GPIO definitions in dlink_dsr-1000n.dts.
- Add more LEDs to the DSR-100n DTS
- Fix off by one in octeon_irq_gpio_map()
- Typo fixes
- Enable SATA by default in cavium_octeon_defconfig
- Support readq/writeq()
- Remove forced mappings of USB interrupts.
- Ensure DMA descriptors are always in the low 4GB
- Improve USB reset code for OCTEON II.
Pistachio:
- Add maintainers entry for pistachio SoC Support
- Remove plat_setup_iocoherency
Ralink:
- Fix pwm UART in spis group pinmux.
SSB:
- Change bare unsigned to unsigned int to suit coding style
Tools:
- Fix reloc tool compiler warnings.
Other:
- Delete use of ARCH_WANT_OPTIONAL_GPIOLIB"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (61 commits)
MIPS: mm: Fix definition of R6 cache instruction
MIPS: tools: Fix relocs tool compiler warnings
MIPS: Cobalt: Fix typo
MIPS: Octeon: Fix typo
MIPS: Lantiq: Fix build failure
MIPS: Use CPHYSADDR to implement mips32 __pa
MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds.
MIPS: Octeon: Clean up GPIO definitions in dlink_dsr-1000n.dts.
MIPS: Octeon: Delete built-in DTB pruning code for D-Link DSR-1000N.
MIPS: store the appended dtb address in a variable
MIPS: ZBOOT: copy appended dtb to the end of the kernel
MIPS: ralink: fix spis group pinmux
MIPS: Factor o32 specific code into signal_o32.c
MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
MIPS: Use per-mm page to execute branch delay slot instructions
MIPS: Modify error handling
MIPS: c-r4k: Use SMP calls for CM indexed cache ops
MIPS: c-r4k: Avoid small flush_icache_range SMP calls
MIPS: c-r4k: Local flush_icache_range cache op override
MIPS: c-r4k: Split r4k_flush_kernel_vmap_range()
...
This commit is contained in:
Linus Torvalds
@@ -127,6 +127,10 @@ extern char arcs_cmdline[COMMAND_LINE_SIZE];
|
||||
*/
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extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
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#ifdef CONFIG_USE_OF
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extern unsigned long fw_passed_dtb;
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#endif
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/*
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* Platform memory detection hook called by setup_arch
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||||
*/
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||||
|
||||
92
arch/mips/include/asm/dsemul.h
Normal file
92
arch/mips/include/asm/dsemul.h
Normal file
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_ASM_DSEMUL_H__
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#define __MIPS_ASM_DSEMUL_H__
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#include <asm/break.h>
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#include <asm/inst.h>
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/* Break instruction with special math emu break code set */
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#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16))
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/* When used as a frame index, indicates the lack of a frame */
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#define BD_EMUFRAME_NONE ((int)BIT(31))
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struct mm_struct;
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struct pt_regs;
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struct task_struct;
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/**
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* mips_dsemul() - 'Emulate' an instruction from a branch delay slot
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* @regs: User thread register context.
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* @ir: The instruction to be 'emulated'.
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* @branch_pc: The PC of the branch instruction.
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* @cont_pc: The PC to continue at following 'emulation'.
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*
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* Emulate or execute an arbitrary MIPS instruction within the context of
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* the current user thread. This is used primarily to handle instructions
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* in the delay slots of emulated branch instructions, for example FP
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* branch instructions on systems without an FPU.
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*
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* Return: Zero on success, negative if ir is a NOP, signal number on failure.
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*/
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extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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unsigned long branch_pc, unsigned long cont_pc);
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|
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/**
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* do_dsemulret() - Return from a delay slot 'emulation' frame
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* @xcp: User thread register context.
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*
|
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* Call in response to the BRK_MEMU break instruction used to return to
|
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* the kernel from branch delay slot 'emulation' frames following a call
|
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* to mips_dsemul(). Restores the user thread PC to the value that was
|
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* passed as the cpc parameter to mips_dsemul().
|
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*
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* Return: True if an emulation frame was returned from, else false.
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*/
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extern bool do_dsemulret(struct pt_regs *xcp);
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/**
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* dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
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* @tsk: The task structure associated with the thread
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*
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* If the thread @tsk has a branch delay slot 'emulation' frame
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* allocated to it then free that frame.
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*
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* Return: True if a frame was freed, else false.
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*/
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extern bool dsemul_thread_cleanup(struct task_struct *tsk);
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/**
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* dsemul_thread_rollback() - Rollback from an 'emulation' frame
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* @regs: User thread register context.
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*
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* If the current thread, whose register context is represented by @regs,
|
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* is executing within a delay slot 'emulation' frame then exit that
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* frame. The PC will be rolled back to the branch if the instruction
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* that was being 'emulated' has not yet executed, or advanced to the
|
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* continuation PC if it has.
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*
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* Return: True if a frame was exited, else false.
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*/
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extern bool dsemul_thread_rollback(struct pt_regs *regs);
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/**
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* dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
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* @mm: The struct mm_struct to cleanup state for.
|
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*
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* Cleanup state for the given @mm, ensuring that any memory allocated
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* for delay slot 'emulation' book-keeping is freed. This is to be called
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* before @mm is freed in order to avoid memory leaks.
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*/
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extern void dsemul_mm_cleanup(struct mm_struct *mm);
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#endif /* __MIPS_ASM_DSEMUL_H__ */
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@@ -458,6 +458,7 @@ extern const char *__elf_platform;
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#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
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#endif
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||||
|
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/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
|
||||
#define ARCH_DLINFO \
|
||||
do { \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, \
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@@ -498,4 +499,7 @@ extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr,
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extern void mips_set_personality_nan(struct arch_elf_state *state);
|
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extern void mips_set_personality_fp(struct arch_elf_state *state);
|
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|
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#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk)
|
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extern int mips_elf_read_implies_exec(void *elf_ex, int exstack);
|
||||
|
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#endif /* _ASM_ELF_H */
|
||||
|
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@@ -24,7 +24,7 @@
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#define _ASM_FPU_EMULATOR_H
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#include <linux/sched.h>
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#include <asm/break.h>
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#include <asm/dsemul.h>
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#include <asm/thread_info.h>
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#include <asm/inst.h>
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#include <asm/local.h>
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@@ -60,27 +60,16 @@ do { \
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#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
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#endif /* CONFIG_DEBUG_FS */
|
||||
|
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extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
|
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unsigned long cpc);
|
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extern int do_dsemulret(struct pt_regs *xcp);
|
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
|
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struct mips_fpu_struct *ctx, int has_fpu,
|
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void *__user *fault_addr);
|
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int process_fpemu_return(int sig, void __user *fault_addr,
|
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unsigned long fcr31);
|
||||
int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
||||
unsigned long *contpc);
|
||||
int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
||||
unsigned long *contpc);
|
||||
|
||||
/*
|
||||
* Instruction inserted following the badinst to further tag the sequence
|
||||
*/
|
||||
#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */
|
||||
|
||||
/*
|
||||
* Break instruction with special math emu break code set
|
||||
*/
|
||||
#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16))
|
||||
|
||||
#define SIGNALLING_NAN 0x7ff800007ff80000LL
|
||||
|
||||
static inline void fpu_emulator_init_fpu(void)
|
||||
|
||||
@@ -42,8 +42,6 @@ enum octeon_irq {
|
||||
OCTEON_IRQ_TIMER1,
|
||||
OCTEON_IRQ_TIMER2,
|
||||
OCTEON_IRQ_TIMER3,
|
||||
OCTEON_IRQ_USB0,
|
||||
OCTEON_IRQ_USB1,
|
||||
#ifndef CONFIG_PCI_MSI
|
||||
OCTEON_IRQ_LAST = 127
|
||||
#endif
|
||||
|
||||
@@ -12,6 +12,14 @@
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
|
||||
static inline bool __should_swizzle_bits(volatile void *a)
|
||||
{
|
||||
extern const bool octeon_should_swizzle_table[];
|
||||
|
||||
unsigned long did = ((unsigned long)a >> 40) & 0xff;
|
||||
return octeon_should_swizzle_table[did];
|
||||
}
|
||||
|
||||
# define __swizzle_addr_b(port) (port)
|
||||
# define __swizzle_addr_w(port) (port)
|
||||
# define __swizzle_addr_l(port) (port)
|
||||
@@ -19,6 +27,8 @@
|
||||
|
||||
#else /* __LITTLE_ENDIAN */
|
||||
|
||||
#define __should_swizzle_bits(a) false
|
||||
|
||||
static inline bool __should_swizzle_addr(unsigned long p)
|
||||
{
|
||||
/* boot bus? */
|
||||
@@ -35,40 +45,14 @@ static inline bool __should_swizzle_addr(unsigned long p)
|
||||
|
||||
#endif /* __BIG_ENDIAN */
|
||||
|
||||
/*
|
||||
* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
|
||||
* less sane hardware forces software to fiddle with this...
|
||||
*
|
||||
* Regardless, if the host bus endianness mismatches that of PCI/ISA, then
|
||||
* you can't have the numerical value of data and byte addresses within
|
||||
* multibyte quantities both preserved at the same time. Hence two
|
||||
* variations of functions: non-prefixed ones that preserve the value
|
||||
* and prefixed ones that preserve byte addresses. The latters are
|
||||
* typically used for moving raw data between a peripheral and memory (cf.
|
||||
* string I/O functions), hence the "__mem_" prefix.
|
||||
*/
|
||||
#if defined(CONFIG_SWAP_IO_SPACE)
|
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|
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# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) le16_to_cpu(x)
|
||||
# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x)
|
||||
# define __mem_ioswabw(a, x) (x)
|
||||
# define ioswabl(a, x) le32_to_cpu(x)
|
||||
# define ioswabl(a, x) (__should_swizzle_bits(a) ? le32_to_cpu(x) : x)
|
||||
# define __mem_ioswabl(a, x) (x)
|
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# define ioswabq(a, x) le64_to_cpu(x)
|
||||
# define ioswabq(a, x) (__should_swizzle_bits(a) ? le64_to_cpu(x) : x)
|
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# define __mem_ioswabq(a, x) (x)
|
||||
|
||||
#else
|
||||
|
||||
# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) (x)
|
||||
# define __mem_ioswabw(a, x) cpu_to_le16(x)
|
||||
# define ioswabl(a, x) (x)
|
||||
# define __mem_ioswabl(a, x) cpu_to_le32(x)
|
||||
# define ioswabq(a, x) (x)
|
||||
# define __mem_ioswabq(a, x) cpu_to_le32(x)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
|
||||
|
||||
@@ -2,11 +2,20 @@
|
||||
#define __ASM_MMU_H
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/wait.h>
|
||||
|
||||
typedef struct {
|
||||
unsigned long asid[NR_CPUS];
|
||||
void *vdso;
|
||||
atomic_t fp_mode_switching;
|
||||
|
||||
/* lock to be held whilst modifying fp_bd_emupage_allocmap */
|
||||
spinlock_t bd_emupage_lock;
|
||||
/* bitmap tracking allocation of fp_bd_emupage */
|
||||
unsigned long *bd_emupage_allocmap;
|
||||
/* wait queue for threads requiring an emuframe */
|
||||
wait_queue_head_t bd_emupage_queue;
|
||||
} mm_context_t;
|
||||
|
||||
#endif /* __ASM_MMU_H */
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/dsemul.h>
|
||||
#include <asm/hazards.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm-generic/mm_hooks.h>
|
||||
@@ -128,6 +129,10 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
||||
|
||||
atomic_set(&mm->context.fp_mode_switching, 0);
|
||||
|
||||
mm->context.bd_emupage_allocmap = NULL;
|
||||
spin_lock_init(&mm->context.bd_emupage_lock);
|
||||
init_waitqueue_head(&mm->context.bd_emupage_queue);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -162,6 +167,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
*/
|
||||
static inline void destroy_context(struct mm_struct *mm)
|
||||
{
|
||||
dsemul_mm_cleanup(mm);
|
||||
}
|
||||
|
||||
#define deactivate_mm(tsk, mm) do { } while (0)
|
||||
|
||||
@@ -168,6 +168,7 @@ static inline unsigned int read_msa_##name(void) \
|
||||
unsigned int reg; \
|
||||
__asm__ __volatile__( \
|
||||
" .set push\n" \
|
||||
" .set fp=64\n" \
|
||||
" .set msa\n" \
|
||||
" cfcmsa %0, $" #cs "\n" \
|
||||
" .set pop\n" \
|
||||
@@ -179,6 +180,7 @@ static inline void write_msa_##name(unsigned int val) \
|
||||
{ \
|
||||
__asm__ __volatile__( \
|
||||
" .set push\n" \
|
||||
" .set fp=64\n" \
|
||||
" .set msa\n" \
|
||||
" ctcmsa $" #cs ", %0\n" \
|
||||
" .set pop\n" \
|
||||
|
||||
@@ -162,16 +162,34 @@ typedef struct { unsigned long pgprot; } pgprot_t;
|
||||
/*
|
||||
* __pa()/__va() should be used only during mem init.
|
||||
*/
|
||||
#ifdef CONFIG_64BIT
|
||||
#define __pa(x) \
|
||||
({ \
|
||||
unsigned long __x = (unsigned long)(x); \
|
||||
__x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \
|
||||
})
|
||||
#else
|
||||
#define __pa(x) \
|
||||
((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
|
||||
#endif
|
||||
static inline unsigned long ___pa(unsigned long x)
|
||||
{
|
||||
if (config_enabled(CONFIG_64BIT)) {
|
||||
/*
|
||||
* For MIPS64 the virtual address may either be in one of
|
||||
* the compatibility segements ckseg0 or ckseg1, or it may
|
||||
* be in xkphys.
|
||||
*/
|
||||
return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
|
||||
}
|
||||
|
||||
if (!config_enabled(CONFIG_EVA)) {
|
||||
/*
|
||||
* We're using the standard MIPS32 legacy memory map, ie.
|
||||
* the address x is going to be in kseg0 or kseg1. We can
|
||||
* handle either case by masking out the desired bits using
|
||||
* CPHYSADDR.
|
||||
*/
|
||||
return CPHYSADDR(x);
|
||||
}
|
||||
|
||||
/*
|
||||
* EVA is in use so the memory map could be anything, making it not
|
||||
* safe to just mask out bits.
|
||||
*/
|
||||
return x - PAGE_OFFSET + PHYS_OFFSET;
|
||||
}
|
||||
#define __pa(x) ___pa((unsigned long)(x))
|
||||
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
|
||||
#include <asm/io.h>
|
||||
|
||||
@@ -229,8 +247,10 @@ extern int __virt_addr_valid(const volatile void *kaddr);
|
||||
#define virt_addr_valid(kaddr) \
|
||||
__virt_addr_valid((const volatile void *) (kaddr))
|
||||
|
||||
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
|
||||
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
|
||||
#define VM_DATA_DEFAULT_FLAGS \
|
||||
(VM_READ | VM_WRITE | \
|
||||
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
|
||||
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
|
||||
|
||||
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
|
||||
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
|
||||
|
||||
@@ -11,12 +11,14 @@
|
||||
#ifndef _ASM_PROCESSOR_H
|
||||
#define _ASM_PROCESSOR_H
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/threads.h>
|
||||
|
||||
#include <asm/cachectl.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/dsemul.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/prefetch.h>
|
||||
|
||||
@@ -78,7 +80,11 @@ extern unsigned int vced_count, vcei_count;
|
||||
|
||||
#endif
|
||||
|
||||
#define STACK_TOP (TASK_SIZE & PAGE_MASK)
|
||||
/*
|
||||
* One page above the stack is used for branch delay slot "emulation".
|
||||
* See dsemul.c for details.
|
||||
*/
|
||||
#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)
|
||||
|
||||
/*
|
||||
* This decides where the kernel will search for a free chunk of vm
|
||||
@@ -256,6 +262,12 @@ struct thread_struct {
|
||||
|
||||
/* Saved fpu/fpu emulator stuff. */
|
||||
struct mips_fpu_struct fpu FPU_ALIGN;
|
||||
/* Assigned branch delay slot 'emulation' frame */
|
||||
atomic_t bd_emu_frame;
|
||||
/* PC of the branch from a branch delay slot 'emulation' */
|
||||
unsigned long bd_emu_branch_pc;
|
||||
/* PC to continue from following a branch delay slot 'emulation' */
|
||||
unsigned long bd_emu_cont_pc;
|
||||
#ifdef CONFIG_MIPS_MT_FPAFF
|
||||
/* Emulated instruction count */
|
||||
unsigned long emulated_fp;
|
||||
@@ -323,6 +335,10 @@ struct thread_struct {
|
||||
* FPU affinity state (null if not FPAFF) \
|
||||
*/ \
|
||||
FPAFF_INIT \
|
||||
/* Delay slot emulation */ \
|
||||
.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
|
||||
.bd_emu_branch_pc = 0, \
|
||||
.bd_emu_cont_pc = 0, \
|
||||
/* \
|
||||
* Saved DSP stuff \
|
||||
*/ \
|
||||
|
||||
@@ -210,7 +210,11 @@ static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||
|
||||
static inline void protected_writeback_scache_line(unsigned long addr)
|
||||
{
|
||||
#ifdef CONFIG_EVA
|
||||
protected_cachee_op(Hit_Writeback_Inv_SD, addr);
|
||||
#else
|
||||
protected_cache_op(Hit_Writeback_Inv_SD, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
|
||||
#include <uapi/asm/signal.h>
|
||||
|
||||
#ifdef CONFIG_MIPS32_COMPAT
|
||||
#ifdef CONFIG_MIPS32_O32
|
||||
extern struct mips_abi mips_abi_32;
|
||||
|
||||
#define sig_uses_siginfo(ka, abi) \
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
extern int smp_num_siblings;
|
||||
extern cpumask_t cpu_sibling_map[];
|
||||
extern cpumask_t cpu_core_map[];
|
||||
extern cpumask_t cpu_foreign_map;
|
||||
extern cpumask_t cpu_foreign_map[];
|
||||
|
||||
#define raw_smp_processor_id() (current_thread_info()->cpu)
|
||||
|
||||
@@ -53,6 +53,8 @@ extern cpumask_t cpu_coherent_mask;
|
||||
|
||||
extern void asmlinkage smp_bootstrap(void);
|
||||
|
||||
extern void calculate_cpu_foreign_map(void);
|
||||
|
||||
/*
|
||||
* this function sends a 'reschedule' IPI to another CPU.
|
||||
* it goes straight through and wastes no time serializing
|
||||
|
||||
Reference in New Issue
Block a user