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drm/amdgpu: iceland use CI based MC IP

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Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Ken Wang 2016-02-03 19:16:54 +08:00 committed by Alex Deucher
parent e42d852616
commit 429c45deae
2 changed files with 13 additions and 4 deletions
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10
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -42,6 +42,7 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
MODULE_FIRMWARE("radeon/bonaire_mc.bin"); MODULE_FIRMWARE("radeon/bonaire_mc.bin");
MODULE_FIRMWARE("radeon/hawaii_mc.bin"); MODULE_FIRMWARE("radeon/hawaii_mc.bin");
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
/** /**
* gmc8_mc_wait_for_idle - wait for MC idle callback. * gmc8_mc_wait_for_idle - wait for MC idle callback.
@ -132,13 +133,20 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
case CHIP_HAWAII: case CHIP_HAWAII:
chip_name = "hawaii"; chip_name = "hawaii";
break; break;
case CHIP_TOPAZ:
chip_name = "topaz";
break;
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_KABINI: case CHIP_KABINI:
return 0; return 0;
default: BUG(); default: BUG();
} }
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); if(adev->asic_type == CHIP_TOPAZ)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
else
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
err = request_firmware(&adev->mc.fw, fw_name, adev->dev); err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
if (err) if (err)
goto out; goto out;

7
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -61,6 +61,7 @@
#include "vi.h" #include "vi.h"
#include "vi_dpm.h" #include "vi_dpm.h"
#include "gmc_v8_0.h" #include "gmc_v8_0.h"
#include "gmc_v7_0.h"
#include "gfx_v8_0.h" #include "gfx_v8_0.h"
#include "sdma_v2_4.h" #include "sdma_v2_4.h"
#include "sdma_v3_0.h" #include "sdma_v3_0.h"
@ -1109,10 +1110,10 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
}, },
{ {
.type = AMD_IP_BLOCK_TYPE_GMC, .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8, .major = 7,
.minor = 0, .minor = 4,
.rev = 0, .rev = 0,
.funcs = &gmc_v8_0_ip_funcs, .funcs = &gmc_v7_0_ip_funcs,
}, },
{ {
.type = AMD_IP_BLOCK_TYPE_IH, .type = AMD_IP_BLOCK_TYPE_IH,