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MIPS: Loongson64: Set IPI_Enable register per core by itself

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In the current code, for example, core 1 sets Core[0, 1, 2, 3]_IPI_Enalbe
register and core 2, 3 do the same thing on the 1-way Loongson64 platform,
this is not necessary. Set IPI_Enable register per core by itself to avoid
duplicate operations and make the logic more clear.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Tiezhu Yang 2020-11-03 15:12:02 +08:00 committed by Thomas Bogendoerfer
parent fe9863a19a
commit 42831cd708
1 changed files with 2 additions and 2 deletions
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4
arch/mips/loongson64/smp.c
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@ -348,8 +348,7 @@ static void loongson3_init_secondary(void)
/* Set interrupt mask, but don't enable */ /* Set interrupt mask, but don't enable */
change_c0_status(ST0_IM, imask); change_c0_status(ST0_IM, imask);
for (i = 0; i < num_possible_cpus(); i++) loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
per_cpu(cpu_state, cpu) = CPU_ONLINE; per_cpu(cpu_state, cpu) = CPU_ONLINE;
cpu_set_core(&cpu_data[cpu], cpu_set_core(&cpu_data[cpu],
@ -420,6 +419,7 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init(); ipi_status0_regs_init();
ipi_en0_regs_init(); ipi_en0_regs_init();
ipi_mailbox_buf_init(); ipi_mailbox_buf_init();
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(0)]);
cpu_set_core(&cpu_data[0], cpu_set_core(&cpu_data[0],
cpu_logical_map(0) % loongson_sysconf.cores_per_package); cpu_logical_map(0) % loongson_sysconf.cores_per_package);
cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;